Commit 9f76e198 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.10' of... 

Merge tag 'phy-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into usb-next

Vinod writes:

phy for 5.9

 - Core:
   - New PHY attribute for max_link_rate

 - New phy drivers:
   - Rockchip dphy driver moved from staging
   - Socionext UniPhier AHCI PHY driver
   - Intel LGM SoC USB phy
   - Intel Keem Bay eMMC PHY driver

 - Updates:
   - Support for imx8mp usb phy
   - Support for DP Phy and USB3+DP combo phy in QMP driver
   - Support for Qualcomm sc7180 DP phy
   - Support for cadence torrent PCIe and USB single linke and multilink
     configurations along with USB, SGMII/QSGMII configurations

* tag 'phy-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits)
  phy: qcom-qmp: initialize the pointer to NULL
  phy: qcom-qmp: Add support for sc7180 DP phy
  phy: qcom-qmp: Add support for DP in USB3+DP combo phy
  phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplify
  phy: qcom-qmp: Get dp_com I/O resource by index
  phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy'
  phy: qcom-qmp: Remove 'initialized' in favor of 'init_count'
  phy: qcom-qmp: Move phy mode into struct qmp_phy
  dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information
  dt-bindings: phy: ti,phy-j721e-wiz: fix bindings for torrent phy
  dt-bindings: phy: cdns,torrent-phy: add reset-names
  phy: rockchip-dphy-rx0: Include linux/delay.h
  phy: fix USB_LGM_PHY warning & build errors
  phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configuration
  phy: cadence-torrent: Add PCIe + USB multilink configuration
  phy: cadence-torrent: Add single link USB register sequences
  phy: cadence-torrent: Add single link SGMII/QSGMII register sequences
  phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals
  phy: cadence-torrent: Add PHY link configuration sequences for single link
  phy: cadence-torrent: Add clk changes for multilink configuration
  ...
parents 37d2a363 60f5a24c

Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt

+1 −1
Original line number Diff line number Diff line 
* Freescale i.MX8MQ USB3 PHY binding



Required properties:

- compatible:	Should be "fsl,imx8mq-usb-phy"

- compatible:	Should be "fsl,imx8mq-usb-phy" or "fsl,imx8mp-usb-phy"

- #phys-cells:	must be 0 (see phy-bindings.txt in this directory)

- reg:		The base address and length of the registers

- clocks:	phandles to the clocks for each clock listed in clock-names

Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml

+16 −1
Original line number Diff line number Diff line
@@ -23,7 +23,9 @@ description: |+ 


properties:

  compatible:

    const: intel,lgm-emmc-phy

    oneOf:

      - const: intel,lgm-emmc-phy

      - const: intel,keembay-emmc-phy



  "#phy-cells":

    const: 0
@@ -34,6 +36,10 @@ properties: 
  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: emmcclk



required:

  - "#phy-cells"

  - compatible
@@ -57,4 +63,13 @@ examples: 
        #phy-cells = <0>;

      };

    };



  - |

    phy@20290000 {

          compatible = "intel,keembay-emmc-phy";

          reg = <0x20290000 0x54>;

          clocks = <&emmc>;

          clock-names = "emmcclk";

          #phy-cells = <0>;

    };

...

Documentation/devicetree/bindings/phy/intel,lgm-usb-phy.yaml

0 → 100644
+58 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/intel,lgm-usb-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel LGM USB PHY Device Tree Bindings



maintainers:

  - Vadivel Murugan Ramuthevar <vadivel.muruganx.ramuthevar@linux.intel.com>



properties:

  compatible:

    const: intel,lgm-usb-phy



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  resets:

    items:

      - description: USB PHY and Host controller reset

      - description: APB BUS reset

      - description: General Hardware reset



  reset-names:

    items:

      - const: phy

      - const: apb

      - const: phy31



  "#phy-cells":

    const: 0



required:

  - compatible

  - clocks

  - reg

  - resets

  - reset-names

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    usb-phy@e7e00000 {

        compatible = "intel,lgm-usb-phy";

        reg = <0xe7e00000 0x10000>;

        clocks = <&cgu0 153>;

        resets = <&rcu 0x70 0x24>,

                 <&rcu 0x70 0x26>,

                 <&rcu 0x70 0x28>;

        reset-names = "phy", "apb", "phy31";

        #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml

+79 −17
Original line number Diff line number Diff line
@@ -4,11 +4,13 @@ 
$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Cadence Torrent SD0801 PHY binding for DisplayPort

title: Cadence Torrent SD0801 PHY binding



description:

  This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)

  hardware included with the Cadence MHDP DisplayPort controller.

  hardware included with the Cadence MHDP DisplayPort controller. Torrent

  PHY also supports multilink multiprotocol combinations including protocols

  such as PCIe, USB, SGMII, QSGMII etc.



maintainers:

  - Swapnil Jakhade <sjakhade@cadence.com>
@@ -49,13 +51,21 @@ properties: 
      - const: dptx_phy



  resets:

    maxItems: 1

    description:

      Torrent PHY reset.

      See Documentation/devicetree/bindings/reset/reset.txt

    minItems: 1

    maxItems: 2

    items:

      - description: Torrent PHY reset.

      - description: Torrent APB reset. This is optional.



  reset-names:

    minItems: 1

    maxItems: 2

    items:

      - const: torrent_reset

      - const: torrent_apb



patternProperties:

  '^phy@[0-7]+$':

  '^phy@[0-3]$':

    type: object

    description:

      Each group of PHY lanes with a single master lane should be represented as a sub-node.
@@ -63,6 +73,8 @@ patternProperties: 
      reg:

        description:

          The master lane number. This is the lowest numbered lane in the lane group.

        minimum: 0

        maximum: 3



      resets:

        minItems: 1
@@ -78,15 +90,25 @@ patternProperties: 
          Specifies the type of PHY for which the group of PHY lanes is used.

          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [1, 2, 3, 4, 5, 6]

        minimum: 1

        maximum: 9



      cdns,num-lanes:

        description:

          Number of DisplayPort lanes.

          Number of lanes.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [1, 2, 4]

        enum: [1, 2, 3, 4]

        default: 4



      cdns,ssc-mode:

        description:

          Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,

          EXTERNAL_SSC or INTERNAL_SSC.

          Refer include/dt-bindings/phy/phy-cadence-torrent.h for the constants to be used.

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [0, 1, 2]

        default: 0



      cdns,max-bit-rate:

        description:

          Maximum DisplayPort link bit rate to use, in Mbps
@@ -99,6 +121,7 @@ patternProperties: 
      - resets

      - "#phy-cells"

      - cdns,phy-type

      - cdns,num-lanes



    additionalProperties: false
@@ -111,6 +134,7 @@ required: 
  - reg

  - reg-names

  - resets

  - reset-names



additionalProperties: false
@@ -128,6 +152,7 @@ examples: 
                  <0xf0 0xfb030a00 0x0 0x00000040>;

            reg-names = "torrent_phy", "dptx_phy";

            resets = <&phyrst 0>;

            reset-names = "torrent_reset";

            clocks = <&ref_clk>;

            clock-names = "refclk";

            #address-cells = <1>;
@@ -143,4 +168,41 @@ examples: 
            };

        };

    };

  - |

    #include <dt-bindings/phy/phy.h>

    #include <dt-bindings/phy/phy-cadence-torrent.h>



    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        torrent-phy@f0fb500000 {

            compatible = "cdns,torrent-phy";

            reg = <0xf0 0xfb500000 0x0 0x00100000>;

            reg-names = "torrent_phy";

            resets = <&phyrst 0>, <&phyrst 1>;

            reset-names = "torrent_reset", "torrent_apb";

            clocks = <&ref_clk>;

            clock-names = "refclk";

            #address-cells = <1>;

            #size-cells = <0>;

            phy@0 {

                reg = <0>;

                resets = <&phyrst 2>, <&phyrst 3>;

                #phy-cells = <0>;

                cdns,phy-type = <PHY_TYPE_PCIE>;

                cdns,num-lanes = <2>;

                cdns,ssc-mode = <TORRENT_SERDES_NO_SSC>;

            };



            phy@2 {

                reg = <2>;

                resets = <&phyrst 4>;

                #phy-cells = <0>;

                cdns,phy-type = <PHY_TYPE_SGMII>;

                cdns,num-lanes = <1>;

                cdns,ssc-mode = <TORRENT_SERDES_NO_SSC>;

            };

        };

    };

...

Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml

+84 −11
Original line number Diff line number Diff line
@@ -13,17 +13,21 @@ maintainers: 
properties:

  compatible:

    enum:

      - qcom,sc7180-qmp-usb3-dp-phy

      - qcom,sc7180-qmp-usb3-phy

      - qcom,sdm845-qmp-usb3-dp-phy

      - qcom,sdm845-qmp-usb3-phy

  reg:

    items:

      - description: Address and length of PHY's common serdes block.

      - description: Address and length of PHY's USB serdes block.

      - description: Address and length of the DP_COM control block.

      - description: Address and length of PHY's DP serdes block.



  reg-names:

    items:

      - const: reg-base

      - const: usb

      - const: dp_com

      - const: dp



  "#clock-cells":

    enum: [ 1, 2 ]
@@ -74,16 +78,74 @@ properties: 


#Required nodes:

patternProperties:

  "^phy@[0-9a-f]+$":

  "^usb3-phy@[0-9a-f]+$":

    type: object

    description:

      Each device node of QMP phy is required to have as many child nodes as

      the number of lanes the PHY has.

      The USB3 PHY.



    properties:

      reg:

        items:

          - description: Address and length of TX.

          - description: Address and length of RX.

          - description: Address and length of PCS.

          - description: Address and length of TX2.

          - description: Address and length of RX2.

          - description: Address and length of pcs_misc.



      clocks:

        items:

          - description: pipe clock



      clock-names:

        items:

          - const: pipe0



      clock-output-names:

        items:

          - const: usb3_phy_pipe_clk_src



      '#clock-cells':

        const: 0



      '#phy-cells':

        const: 0



    required:

      - reg

      - clocks

      - clock-names

      - '#clock-cells'

      - '#phy-cells'



  "^dp-phy@[0-9a-f]+$":

    type: object

    description:

      The DP PHY.



    properties:

      reg:

        items:

          - description: Address and length of TX.

          - description: Address and length of RX.

          - description: Address and length of PCS.

          - description: Address and length of TX2.

          - description: Address and length of RX2.



      '#clock-cells':

        const: 1



      '#phy-cells':

        const: 0



    required:

      - reg

      - '#clock-cells'

      - '#phy-cells'



required:

  - compatible

  - reg

  - reg-names

  - "#clock-cells"

  - "#address-cells"

  - "#size-cells"
@@ -101,14 +163,15 @@ examples: 
  - |

    #include <dt-bindings/clock/qcom,gcc-sdm845.h>

    usb_1_qmpphy: phy-wrapper@88e9000 {

        compatible = "qcom,sdm845-qmp-usb3-phy";

        compatible = "qcom,sdm845-qmp-usb3-dp-phy";

        reg = <0x088e9000 0x18c>,

              <0x088e8000 0x10>;

        reg-names = "reg-base", "dp_com";

              <0x088e8000 0x10>,

              <0x088ea000 0x40>;

        reg-names = "usb", "dp_com", "dp";

        #clock-cells = <1>;

        #address-cells = <1>;

        #size-cells = <1>;

        ranges = <0x0 0x088e9000 0x1000>;

        ranges = <0x0 0x088e9000 0x2000>;



        clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
@@ -123,7 +186,7 @@ examples: 
        vdda-phy-supply = <&vdda_usb2_ss_1p2>;

        vdda-pll-supply = <&vdda_usb2_ss_core>;



        phy@200 {

        usb3-phy@200 {

            reg = <0x200 0x128>,

                  <0x400 0x200>,

                  <0xc00 0x218>,
@@ -136,4 +199,14 @@ examples: 
            clock-names = "pipe0";

            clock-output-names = "usb3_phy_pipe_clk_src";

        };



        dp-phy@88ea200 {

            reg = <0xa200 0x200>,

                  <0xa400 0x200>,

                  <0xaa00 0x200>,

                  <0xa600 0x200>,

                  <0xa800 0x200>;

            #clock-cells = <1>;

            #phy-cells = <0>;

        };

    };

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