Commit 9cf0418e authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'vexpress-drm-arm-soc' of... 

Merge tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt

Versatile Express DTS update for DRM:
This updates the Versatile Express family DTS files to
contain the correct and detailed information required
for the PL11x DRM driver to work properly.

* tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator

:
  ARM: dts: Modernize the Vexpress PL111 integration

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents d3e9d2ce f1fe12c8

arch/arm/boot/dts/vexpress-v2m-rs1.dtsi

+17 −32
Original line number Diff line number Diff line
@@ -43,11 +43,6 @@ 
				bank-width = <4>;

			};



			v2m_video_ram: vram@2,00000000 {

				compatible = "arm,vexpress-vram";

				reg = <2 0x00000000 0x00800000>;

			};



			ethernet@2,02000000 {

				compatible = "smsc,lan9118", "smsc,lan9115";

				reg = <2 0x02000000 0x10000>;
@@ -223,13 +218,24 @@ 
				v2m_i2c_dvi: i2c@160000 {

					compatible = "arm,versatile-i2c";

					reg = <0x160000 0x1000>;



					#address-cells = <1>;

					#size-cells = <0>;



					dvi-transmitter@39 {

						compatible = "sil,sii9022-tpi", "sil,sii9022";

						reg = <0x39>;



						ports {

							#address-cells = <1>;

							#size-cells = <0>;



							port@0 {

								reg = <0>;

								dvi_bridge_in: endpoint {

									remote-endpoint = <&clcd_pads>;

								};

							};

						};

					};



					dvi-transmitter@60 {
@@ -260,37 +266,16 @@ 
					interrupts = <14>;

					clocks = <&v2m_oscclk1>, <&smbclk>;

					clock-names = "clcdclk", "apb_pclk";

					memory-region = <&v2m_video_ram>;

					max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */

					/* 800x600 16bpp @36MHz works fine */

					max-memory-bandwidth = <54000000>;

					memory-region = <&vram>;



					port {

						v2m_clcd_pads: endpoint {

							remote-endpoint = <&v2m_clcd_panel>;

						clcd_pads: endpoint {

							remote-endpoint = <&dvi_bridge_in>;

							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;

						};

					};



					panel {

						compatible = "panel-dpi";



						port {

							v2m_clcd_panel: endpoint {

								remote-endpoint = <&v2m_clcd_pads>;

							};

						};



						panel-timing {

							clock-frequency = <25175000>;

							hactive = <640>;

							hback-porch = <40>;

							hfront-porch = <24>;

							hsync-len = <96>;

							vactive = <480>;

							vback-porch = <32>;

							vfront-porch = <11>;

							vsync-len = <2>;

						};

					};

				};

			};

arch/arm/boot/dts/vexpress-v2m.dtsi

+31 −32
Original line number Diff line number Diff line
@@ -43,11 +43,6 @@ 
				bank-width = <4>;

			};



			v2m_video_ram: vram@3,00000000 {

				compatible = "arm,vexpress-vram";

				reg = <3 0x00000000 0x00800000>;

			};



			ethernet@3,02000000 {

				compatible = "smsc,lan9118", "smsc,lan9115";

				reg = <3 0x02000000 0x10000>;
@@ -223,13 +218,37 @@ 
				v2m_i2c_dvi: i2c@16000 {

					compatible = "arm,versatile-i2c";

					reg = <0x16000 0x1000>;



					#address-cells = <1>;

					#size-cells = <0>;



					dvi-transmitter@39 {

						compatible = "sil,sii9022-tpi", "sil,sii9022";

						reg = <0x39>;



						ports {

							#address-cells = <1>;

							#size-cells = <0>;



							/*

							 * Both the core tile and the motherboard routes their output

							 * pads to this transmitter. The motherboard system controller

							 * can select one of them as input using a mux register in

							 * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is

							 * the only platform with this specific set-up.

							 */

							port@0 {

								reg = <0>;

								dvi_bridge_in_ct: endpoint {

									remote-endpoint = <&clcd_pads_ct>;

								};

							};

							port@1 {

								reg = <1>;

								dvi_bridge_in_mb: endpoint {

									remote-endpoint = <&clcd_pads_mb>;

								};

							};

						};

					};



					dvi-transmitter@60 {
@@ -253,6 +272,7 @@ 
					reg-shift = <2>;

				};





				clcd@1f000 {

					compatible = "arm,pl111", "arm,primecell";

					reg = <0x1f000 0x1000>;
@@ -260,37 +280,16 @@ 
					interrupts = <14>;

					clocks = <&v2m_oscclk1>, <&smbclk>;

					clock-names = "clcdclk", "apb_pclk";

					memory-region = <&v2m_video_ram>;

					max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */

					/* 800x600 16bpp @36MHz works fine */

					max-memory-bandwidth = <54000000>;

					memory-region = <&vram>;



					port {

						v2m_clcd_pads: endpoint {

							remote-endpoint = <&v2m_clcd_panel>;

						clcd_pads_mb: endpoint {

							remote-endpoint = <&dvi_bridge_in_mb>;

							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;

						};

					};



					panel {

						compatible = "panel-dpi";



						port {

							v2m_clcd_panel: endpoint {

								remote-endpoint = <&v2m_clcd_pads>;

							};

						};



						panel-timing {

							clock-frequency = <25175000>;

							hactive = <640>;

							hback-porch = <40>;

							hfront-porch = <24>;

							hsync-len = <96>;

							vactive = <480>;

							vback-porch = <32>;

							vfront-porch = <11>;

							vsync-len = <2>;

						};

					};

				};

			};

arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts

+14 −0
Original line number Diff line number Diff line
@@ -53,6 +53,20 @@ 
		reg = <0 0x80000000 0 0x40000000>;

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		/* Chipselect 2 is physically at 0x18000000 */

		vram: vram@18000000 {

			/* 8 MB of designated video RAM */

			compatible = "shared-dma-pool";

			reg = <0 0x18000000 0 0x00800000>;

			no-map;

		};

	};



	hdlcd@2b000000 {

		compatible = "arm,hdlcd";

		reg = <0 0x2b000000 0 0x1000>;

arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

+14 −0
Original line number Diff line number Diff line
@@ -104,6 +104,20 @@ 
		reg = <0 0x80000000 0 0x40000000>;

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		/* Chipselect 2 is physically at 0x18000000 */

		vram: vram@18000000 {

			/* 8 MB of designated video RAM */

			compatible = "shared-dma-pool";

			reg = <0 0x18000000 0 0x00800000>;

			no-map;

		};

	};



	wdt@2a490000 {

		compatible = "arm,sp805", "arm,primecell";

		reg = <0 0x2a490000 0 0x1000>;

arch/arm/boot/dts/vexpress-v2p-ca5s.dts

+14 −0
Original line number Diff line number Diff line
@@ -55,6 +55,20 @@ 
		reg = <0x80000000 0x40000000>;

	};



	reserved-memory {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		/* Chipselect 2 is physically at 0x18000000 */

		vram: vram@18000000 {

			/* 8 MB of designated video RAM */

			compatible = "shared-dma-pool";

			reg = <0x18000000 0x00800000>;

			no-map;

		};

	};



	hdlcd@2a110000 {

		compatible = "arm,hdlcd";

		reg = <0x2a110000 0x1000>;

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