ARM: dts: mmp2: Add SSP controllers (d3e9d2ce) · Commits · 戴 / test

Despite Marvel keeps their base addresses secret there's a good chance they're actually correct. SSP1 and SSP3 bases were taken from OLPC 1.75: OpenFirmware and kernel respectively. SSP2 and SSP4 addresses are from James Cameron who actually has a copy of the data sheet. Signed-off-by:

Lubomir Rintel <lkundrak@v3.sk> Acked-by:

Pavel Machek <pavel@ucw.cz> Signed-off-by:

Olof Johansson <olof@lixom.net>

arch/arm/boot/dts/mmp2.dtsi

+32 −0

Original line number	Diff line number	Diff line
		@@ -346,6 +346,38 @@
		resets = <&soc_clocks MMP2_CLK_RTC>;
		status = "disabled";
		};

		ssp1: ssp@d4035000 {
		compatible = "marvell,mmp2-ssp";
		reg = <0xd4035000 0x1000>;
		clocks = <&soc_clocks MMP2_CLK_SSP0>;
		interrupts = <0>;
		status = "disabled";
		};

		ssp2: ssp@d4036000 {
		compatible = "marvell,mmp2-ssp";
		reg = <0xd4036000 0x1000>;
		clocks = <&soc_clocks MMP2_CLK_SSP1>;
		interrupts = <1>;
		status = "disabled";
		};

		ssp3: ssp@d4037000 {
		compatible = "marvell,mmp2-ssp";
		reg = <0xd4037000 0x1000>;
		clocks = <&soc_clocks MMP2_CLK_SSP2>;
		interrupts = <20>;
		status = "disabled";
		};

		ssp4: ssp@d4039000 {
		compatible = "marvell,mmp2-ssp";
		reg = <0xd4039000 0x1000>;
		clocks = <&soc_clocks MMP2_CLK_SSP3>;
		interrupts = <21>;
		status = "disabled";
		};
		};

		soc_clocks: clocks{

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