Commit 9c644f83 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-5.3-arm64-dt' of... 

Merge tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.3-rc1

This contains the bulk of the Tegra changes this cycle. It has a bunch
of improvements across almost all boards. These are mostly small and not
too exciting additions.

Most notably perhaps is the continuation of Jetson Nano support, which
is now mostly on feature parity with Jetson TX1.

* tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

: (28 commits)
  arm64: tegra: Enable PCIe slots in P2972-0000 board
  arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
  arm64: tegra: Add PEX DPD states as pinctrl properties
  arm64: tegra: Enable ACONNECT, ADMA and AGIC
  arm64: tegra: Add ACONNECT, ADMA and AGIC nodes
  arm64: tegra: Sort device tree nodes alphabetically
  arm64: tegra: Fix Jetson Nano GPU regulator
  arm64: tegra: Update Jetson TX1 GPU regulator timings
  arm64: tegra: Fix AGIC register range
  arm64: tegra: Add INA3221 channel info for Jetson TX2
  arm64: tegra: Enable PWM on Jetson Nano
  arm64: tegra: Enable CPU sleep on Jetson Nano
  arm64: tegra: Add ID EEPROMs on Jetson Nano
  arm64: tegra: Add ID EEPROM for Jetson TX2 Developer Kit
  arm64: tegra: Add ID EEPROM for Jetson TX2 module
  arm64: tegra: Add ID EEPROM for Jetson TX1 Developer Kit
  arm64: tegra: Add ID EEPROM for Jetson TX1 module
  arm64: tegra: Don't use architected timer for suspend on Tegra210
  arm64: tegra: Mark architected timer as always on
  arm64: tegra: Add pin control states for I2C on Tegra186
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents b9569a3c a586c88e

arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts

+72 −3
Original line number Diff line number Diff line
@@ -7,18 +7,70 @@ 
#include "tegra186-p3310.dtsi"



/ {

	model = "NVIDIA Tegra186 P2771-0000 Development Board";

	model = "NVIDIA Jetson TX2 Developer Kit";

	compatible = "nvidia,p2771-0000", "nvidia,tegra186";



	aconnect {

		status = "okay";



		dma-controller@2930000 {

			status = "okay";

		};



		interrupt-controller@2a40000 {

			status = "okay";

		};

	};



	i2c@3160000 {

		power-monitor@42 {

			compatible = "ti,ina3221";

			reg = <0x42>;

			#address-cells = <1>;

			#size-cells = <0>;



			channel@0 {

				reg = <0x0>;

				label = "VDD_MUX";

				shunt-resistor-micro-ohms = <20000>;

			};



			channel@1 {

				reg = <0x1>;

				label = "VDD_5V0_IO_SYS";

				shunt-resistor-micro-ohms = <5000>;

			};



			channel@2 {

				reg = <0x2>;

				label = "VDD_3V3_SYS";

				shunt-resistor-micro-ohms = <10000>;

			};

		};



		power-monitor@43 {

			compatible = "ti,ina3221";

			reg = <0x43>;

			#address-cells = <1>;

			#size-cells = <0>;



			channel@0 {

				reg = <0x0>;

				label = "VDD_3V3_IO_SLP";

				shunt-resistor-micro-ohms = <10000>;

			};



			channel@1 {

				reg = <0x1>;

				label = "VDD_1V8_IO";

				shunt-resistor-micro-ohms = <10000>;

			};



			channel@2 {

				reg = <0x2>;

				label = "VDD_M2_IN";

				shunt-resistor-micro-ohms = <10000>;

			};

		};



		exp1: gpio@74 {
@@ -31,6 +83,8 @@ 


			#gpio-cells = <2>;

			gpio-controller;



			vcc-supply = <&vdd_3v3_sys>;

		};



		exp2: gpio@77 {
@@ -43,6 +97,8 @@ 


			#gpio-cells = <2>;

			gpio-controller;



			vcc-supply = <&vdd_1v8>;

		};

	};
@@ -145,6 +201,19 @@ 
		phy-names = "usb2-0", "usb2-1", "usb3-0";

	};



	i2c@c250000 {

		/* carrier board ID EEPROM */

		eeprom@57 {

			compatible = "atmel,24c02";

			reg = <0x57>;



			address-bits = <8>;

			page-size = <8>;

			size = <256>;

			read-only;

		};

	};



	pcie@10003000 {

		status = "okay";
@@ -278,7 +347,7 @@ 
			regulator-min-microvolt = <5000000>;

			regulator-max-microvolt = <5000000>;



			gpio = <&gpio TEGRA_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;

			gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>;

			enable-active-high;



			vin-supply = <&vdd_5v0_sys>;
@@ -292,7 +361,7 @@ 
			regulator-min-microvolt = <5000000>;

			regulator-max-microvolt = <5000000>;



			gpio = <&gpio TEGRA_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;

			gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>;

			enable-active-high;



			vin-supply = <&vdd_5v0_sys>;

arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi

+52 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
#include <dt-bindings/mfd/max77620.h>



/ {

	model = "NVIDIA Tegra186 P3310 Processor Module";

	model = "NVIDIA Jetson TX2";

	compatible = "nvidia,p3310", "nvidia,tegra186";



	aliases {
@@ -67,11 +67,51 @@ 
		power-monitor@40 {

			compatible = "ti,ina3221";

			reg = <0x40>;

			#address-cells = <1>;

			#size-cells = <0>;



			channel@0 {

				reg = <0x0>;

				label = "VDD_SYS_GPU";

				shunt-resistor-micro-ohms = <10000>;

			};



			channel@1 {

				reg = <0x1>;

				label = "VDD_SYS_SOC";

				shunt-resistor-micro-ohms = <10000>;

			};



			channel@2 {

				reg = <0x2>;

				label = "VDD_3V8_WIFI";

				shunt-resistor-micro-ohms = <10000>;

			};

		};



		power-monitor@41 {

			compatible = "ti,ina3221";

			reg = <0x41>;

			#address-cells = <1>;

			#size-cells = <0>;



			channel@0 {

				reg = <0x0>;

				label = "VDD_IN";

				shunt-resistor-micro-ohms = <5000>;

			};



			channel@1 {

				reg = <0x1>;

				label = "VDD_SYS_CPU";

				shunt-resistor-micro-ohms = <10000>;

			};



			channel@2 {

				reg = <0x2>;

				label = "VDD_5V0_DDR";

				shunt-resistor-micro-ohms = <10000>;

			};

		};

	};
@@ -124,6 +164,17 @@ 


	i2c@c250000 {

		status = "okay";



		/* module ID EEPROM */

		eeprom@50 {

			compatible = "atmel,24c02";

			reg = <0x50>;



			address-bits = <8>;

			page-size = <8>;

			size = <256>;

			read-only;

		};

	};



	rtc@c2a0000 {

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+156 −20
Original line number Diff line number Diff line
@@ -70,6 +70,75 @@ 
		snps,rxpbl = <8>;

	};



	aconnect {

		compatible = "nvidia,tegra186-aconnect",

			     "nvidia,tegra210-aconnect";

		clocks = <&bpmp TEGRA186_CLK_APE>,

			 <&bpmp TEGRA186_CLK_APB2APE>;

		clock-names = "ape", "apb2ape";

		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x02900000 0x0 0x02900000 0x200000>;

		status = "disabled";



		dma-controller@2930000 {

			compatible = "nvidia,tegra186-adma";

			reg = <0x02930000 0x20000>;

			interrupt-parent = <&agic>;

			interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

			#dma-cells = <1>;

			clocks = <&bpmp TEGRA186_CLK_AHUB>;

			clock-names = "d_audio";

			status = "disabled";

		};



		agic: interrupt-controller@2a40000 {

			compatible = "nvidia,tegra186-agic",

				     "nvidia,tegra210-agic";

			#interrupt-cells = <3>;

			interrupt-controller;

			reg = <0x02a41000 0x1000>,

			      <0x02a42000 0x2000>;

			interrupts = <GIC_SPI 145

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

			clocks = <&bpmp TEGRA186_CLK_APE>;

			clock-names = "clk";

			status = "disabled";

		};

	};



	memory-controller@2c00000 {

		compatible = "nvidia,tegra186-mc";

		reg = <0x0 0x02c00000 0x0 0xb0000>;
@@ -173,6 +242,9 @@ 
		clock-names = "div-clk";

		resets = <&bpmp TEGRA186_RESET_I2C4>;

		reset-names = "i2c";

		pinctrl-names = "default", "idle";

		pinctrl-0 = <&state_dpaux1_i2c>;

		pinctrl-1 = <&state_dpaux1_off>;

		status = "disabled";

	};
@@ -201,6 +273,9 @@ 
		clock-names = "div-clk";

		resets = <&bpmp TEGRA186_RESET_I2C6>;

		reset-names = "i2c";

		pinctrl-names = "default", "idle";

		pinctrl-0 = <&state_dpaux_i2c>;

		pinctrl-1 = <&state_dpaux_off>;

		status = "disabled";

	};
@@ -1121,6 +1196,30 @@ 
		};

	};



	bpmp: bpmp {

		compatible = "nvidia,tegra186-bpmp";

		iommus = <&smmu TEGRA186_SID_BPMP>;

		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB

				    TEGRA_HSP_DB_MASTER_BPMP>;

		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;

		#clock-cells = <1>;

		#reset-cells = <1>;

		#power-domain-cells = <1>;



		bpmp_i2c: i2c {

			compatible = "nvidia,tegra186-bpmp-i2c";

			nvidia,bpmp-bus-id = <5>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		bpmp_thermal: thermal {

			compatible = "nvidia,tegra186-bpmp-thermal";

			#thermal-sensor-cells = <1>;

		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -1128,61 +1227,97 @@ 
		cpu@0 {

			compatible = "nvidia,tegra186-denver";

			device_type = "cpu";

			i-cache-size = <0x20000>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <0x10000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_DENVER>;

			reg = <0x000>;

		};



		cpu@1 {

			compatible = "nvidia,tegra186-denver";

			device_type = "cpu";

			i-cache-size = <0x20000>;

			i-cache-line-size = <64>;

			i-cache-sets = <512>;

			d-cache-size = <0x10000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_DENVER>;

			reg = <0x001>;

		};



		cpu@2 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_A57>;

			reg = <0x100>;

		};



		cpu@3 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_A57>;

			reg = <0x101>;

		};



		cpu@4 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_A57>;

			reg = <0x102>;

		};



		cpu@5 {

			compatible = "arm,cortex-a57";

			device_type = "cpu";

			i-cache-size = <0xC000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&L2_A57>;

			reg = <0x103>;

		};

	};



	bpmp: bpmp {

		compatible = "nvidia,tegra186-bpmp";

		iommus = <&smmu TEGRA186_SID_BPMP>;

		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB

				    TEGRA_HSP_DB_MASTER_BPMP>;

		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;

		#clock-cells = <1>;

		#reset-cells = <1>;

		#power-domain-cells = <1>;



		bpmp_i2c: i2c {

			compatible = "nvidia,tegra186-bpmp-i2c";

			nvidia,bpmp-bus-id = <5>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		L2_DENVER: l2-cache0 {

			compatible = "cache";

			cache-unified;

			cache-level = <2>;

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;

		};



		bpmp_thermal: thermal {

			compatible = "nvidia,tegra186-bpmp-thermal";

			#thermal-sensor-cells = <1>;

		L2_A57: l2-cache1 {

			compatible = "cache";

			cache-unified;

			cache-level = <2>;

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;

		};

	};
@@ -1294,5 +1429,6 @@ 
			     <GIC_PPI 10

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		interrupt-parent = <&gic>;

		always-on;

	};

};

arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
#include <dt-bindings/mfd/max77620.h>



/ {

	model = "NVIDIA Tegra194 P2888 Processor Module";

	model = "NVIDIA Jetson AGX Xavier";

	compatible = "nvidia,p2888", "nvidia,tegra194";



	aliases {
@@ -191,7 +191,7 @@ 
						regulator-boot-on;

					};



					sd3 {

					vdd_1v8ao: sd3 {

						regulator-name = "VDD_1V8AO";

						regulator-min-microvolt = <1800000>;

						regulator-max-microvolt = <1800000>;

arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts

+54 −1
Original line number Diff line number Diff line
@@ -7,10 +7,22 @@ 
#include "tegra194-p2888.dtsi"



/ {

	model = "NVIDIA Jetson AGX Xavier Development Kit";

	model = "NVIDIA Jetson AGX Xavier Developer Kit";

	compatible = "nvidia,p2972-0000", "nvidia,tegra194";



	cbb {

		aconnect {

			status = "okay";



			dma-controller@2930000 {

				status = "okay";

			};



			interrupt-controller@2a40000 {

				status = "okay";

			};

		};



		ddc: i2c@31c0000 {

			status = "okay";

		};
@@ -52,6 +64,47 @@ 
		};

	};



	pcie@14100000 {

		status = "okay";



		vddio-pex-ctl-supply = <&vdd_1v8ao>;



		phys = <&p2u_hsio_0>;

		phy-names = "p2u-0";

	};



	pcie@14140000 {

		status = "okay";



		vddio-pex-ctl-supply = <&vdd_1v8ao>;



		phys = <&p2u_hsio_7>;

		phy-names = "p2u-0";

	};



	pcie@14180000 {

		status = "okay";



		vddio-pex-ctl-supply = <&vdd_1v8ao>;



		phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,

		       <&p2u_hsio_5>;

		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";

	};



	pcie@141a0000 {

		status = "disabled";



		vddio-pex-ctl-supply = <&vdd_1v8ao>;



		phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,

		       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,

		       <&p2u_nvhs_6>, <&p2u_nvhs_7>;



		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",

			    "p2u-5", "p2u-6", "p2u-7";

	};



	fan: fan {

		compatible = "pwm-fan";

		pwms = <&pwm4 0 45334>;

CRA Git | Maintained and supported by SUSTech CRA and CCSE