drm/amdgpu: abstract gart aperture initialization for gfxhub/mmhub (9bbad6fd) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+20 −17

Original line number	Diff line number	Diff line
		@@ -55,6 +55,25 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
		upper_32_bits(value));
		}

		static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
		{
		gfxhub_v1_0_init_gart_pt_regs(adev);

		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
		(u32)(adev->mc.gtt_start >> 12));
		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
		(u32)(adev->mc.gtt_start >> 44));

		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
		(u32)(adev->mc.gtt_end >> 12));
		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
		(u32)(adev->mc.gtt_end >> 44));
		}

		int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
		{
		u32 tmp;
		@@ -62,9 +81,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
		u32 i;

		/* Program MC. */
		gfxhub_v1_0_init_gart_pt_regs(adev);
		gfxhub_v1_0_init_gart_aperture_regs(adev);

		/* Update configuration */
		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
		adev->mc.vram_start >> 18);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
		@@ -165,21 +183,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
		0);
		WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);

		/* setup context0 */
		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
		(u32)(adev->mc.gtt_start >> 12));
		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
		(u32)(adev->mc.gtt_start >> 44));

		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
		(u32)(adev->mc.gtt_end >> 12));
		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
		(u32)(adev->mc.gtt_end >> 44));

		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
		(u32)(adev->dummy_page.addr >> 12));

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+20 −15

Original line number	Diff line number	Diff line
		@@ -66,6 +66,25 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
		upper_32_bits(value));
		}

		static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
		{
		mmhub_v1_0_init_gart_pt_regs(adev);

		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
		(u32)(adev->mc.gtt_start >> 12));
		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
		(u32)(adev->mc.gtt_start >> 44));

		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
		(u32)(adev->mc.gtt_end >> 12));
		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
		(u32)(adev->mc.gtt_end >> 44));
		}

		int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
		{
		u32 tmp;
		@@ -75,6 +94,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)

		/* Program MC. */
		mmhub_v1_0_init_gart_pt_regs(adev);
		mmhub_v1_0_init_gart_aperture_regs(adev);

		/* Update configuration */
		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
		@@ -176,21 +196,6 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
		0);
		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);

		/* setup context0 */
		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
		(u32)(adev->mc.gtt_start >> 12));
		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
		(u32)(adev->mc.gtt_start >> 44));

		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
		(u32)(adev->mc.gtt_end >> 12));
		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
		(u32)(adev->mc.gtt_end >> 44));

		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
		(u32)(adev->dummy_page.addr >> 12));

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