drm/amdgpu: abstract gart table initialization for gfxhub/mmhub (a51dca4f) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+21 −13

Original line number	Diff line number	Diff line
		@@ -36,6 +36,25 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
		return (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_OFFSET)) << 24;
		}

		static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
		{
		uint64_t value;

		BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
		value = adev->gart.table_addr - adev->mc.vram_start
		+ adev->vm_manager.vram_base_offset;
		value &= 0x0000FFFFFFFFF000ULL;
		value \|= 0x1; /valid bit/

		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
		lower_32_bits(value));

		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
		upper_32_bits(value));
		}

		int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
		{
		u32 tmp;
		@@ -43,6 +62,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
		u32 i;

		/* Program MC. */
		gfxhub_v1_0_init_gart_pt_regs(adev);

		/* Update configuration */
		WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
		adev->mc.vram_start >> 18);
		@@ -159,19 +180,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
		mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
		(u32)(adev->mc.gtt_end >> 44));

		BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
		value = adev->gart.table_addr - adev->mc.vram_start
		+ adev->vm_manager.vram_base_offset;
		value &= 0x0000FFFFFFFFF000ULL;
		value \|= 0x1; /valid bit/

		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
		(u32)value);
		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
		(u32)(value >> 32));

		WREG32(SOC15_REG_OFFSET(GC, 0,
		mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
		(u32)(adev->dummy_page.addr >> 12));

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+21 −13

Original line number	Diff line number	Diff line
		@@ -47,6 +47,25 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
		return base;
		}

		static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
		{
		uint64_t value;

		BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
		value = adev->gart.table_addr - adev->mc.vram_start +
		adev->vm_manager.vram_base_offset;
		value &= 0x0000FFFFFFFFF000ULL;
		value \|= 0x1; /* valid bit */

		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
		lower_32_bits(value));

		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
		upper_32_bits(value));
		}

		int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
		{
		u32 tmp;
		@@ -55,6 +74,8 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
		u32 i;

		/* Program MC. */
		mmhub_v1_0_init_gart_pt_regs(adev);

		/* Update configuration */
		WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
		adev->mc.vram_start >> 18);
		@@ -170,19 +191,6 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
		mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
		(u32)(adev->mc.gtt_end >> 44));

		BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
		value = adev->gart.table_addr - adev->mc.vram_start +
		adev->vm_manager.vram_base_offset;
		value &= 0x0000FFFFFFFFF000ULL;
		value \|= 0x1; /* valid bit */

		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
		(u32)value);
		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
		(u32)(value >> 32));

		WREG32(SOC15_REG_OFFSET(MMHUB, 0,
		mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
		(u32)(adev->dummy_page.addr >> 12));

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