Commit 99739f94 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915/tgl: Keep FF dop clock enabled for A0 



To ensure correct state data for compute workloads, we
need to keep the ff dop clock enabled.

References: HSDES#1606700617
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-5-mika.kuoppala@linux.intel.com
parent 36a6b5d9

drivers/gpu/drm/i915/gt/intel_workarounds.c

+8 −1
Original line number Diff line number Diff line
@@ -567,7 +567,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,

				     struct i915_wa_list *wal)

{

	/* Wa_1409142259 */

	/* Wa_1409142259:tgl */

	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,

			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);

}
@@ -1265,6 +1265,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
{

	struct drm_i915_private *i915 = engine->i915;



	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {

		/* Wa_1606700617:tgl */

		wa_masked_en(wal,

			     GEN9_CS_DEBUG_MODE1,

			     FF_DOP_CLOCK_GATE_DISABLE);

	}



	if (IS_GEN(i915, 11)) {

		/* This is not an Wa. Enable for better image quality */

		wa_masked_en(wal,

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -7673,6 +7673,7 @@ enum { 
#define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1 << 10)



#define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)

#define   FF_DOP_CLOCK_GATE_DISABLE	REG_BIT(1)

#define GEN9_CTX_PREEMPT_REG		_MMIO(0x2248)

#define GEN8_CS_CHICKEN1		_MMIO(0x2580)

#define GEN9_PREEMPT_3D_OBJECT_LEVEL		(1 << 0)

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