drm/i915/tgl: Add extra hdc flush workaround (36a6b5d9) · Commits · 戴 / test

In order to ensure constant caches are invalidated properly with a0, we need extra hdc flush after invalidation. v2: use IS_TGL_REVID (Chris) References: HSDES#1604544889 Signed-off-by:

Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:

Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:

Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-4-mika.kuoppala@linux.intel.com

drivers/gpu/drm/i915/gt/intel_lrc.c

+20 −0

Original line number	Diff line number	Diff line
		@@ -3253,6 +3253,26 @@ static int gen12_emit_flush_render(struct i915_request *request,

		*cs++ = preparser_disable(false);
		intel_ring_advance(request, cs);

		/*
		* Wa_1604544889:tgl
		*/
		if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
		flags = 0;
		flags \|= PIPE_CONTROL_CS_STALL;
		flags \|= PIPE_CONTROL_HDC_PIPELINE_FLUSH;

		flags \|= PIPE_CONTROL_STORE_DATA_INDEX;
		flags \|= PIPE_CONTROL_QW_WRITE;

		cs = intel_ring_begin(request, 6);
		if (IS_ERR(cs))
		return PTR_ERR(cs);

		cs = gen8_emit_pipe_control(cs, flags,
		LRC_PPHWSP_SCRATCH_ADDR);
		intel_ring_advance(request, cs);
		}
		}

		return 0;

Admin message