Commit 4aa0b5d4 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915/tgl: Add HDC Pipeline Flush 



Add hdc pipeline flush to ensure memory state is coherent
in L3 when we are done.

v2: Flush also in breadcrumbs (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-3-mika.kuoppala@linux.intel.com
parent 62037fff

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

+1 −0
Original line number Diff line number Diff line
@@ -235,6 +235,7 @@ 
#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */

#define   PIPE_CONTROL_L3_RO_CACHE_INVALIDATE		REG_BIT(10) /* gen12 */

#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)

#define   PIPE_CONTROL_HDC_PIPELINE_FLUSH		REG_BIT(9)  /* gen12 */

#define   PIPE_CONTROL_NOTIFY				(1<<8)

#define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */

#define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)

drivers/gpu/drm/i915/gt/intel_lrc.c

+3 −1
Original line number Diff line number Diff line
@@ -3205,6 +3205,7 @@ static int gen12_emit_flush_render(struct i915_request *request, 
		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;

		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;

		flags |= PIPE_CONTROL_FLUSH_ENABLE;

		flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;



		flags |= PIPE_CONTROL_STORE_DATA_INDEX;

		flags |= PIPE_CONTROL_QW_WRITE;
@@ -3415,7 +3416,8 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) 
				      PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |

				      PIPE_CONTROL_DEPTH_CACHE_FLUSH |

				      PIPE_CONTROL_DC_FLUSH_ENABLE |

				      PIPE_CONTROL_FLUSH_ENABLE);

				      PIPE_CONTROL_FLUSH_ENABLE |

				      PIPE_CONTROL_HDC_PIPELINE_FLUSH);



	return gen12_emit_fini_breadcrumb_footer(request, cs);

}

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