Commit 992fbe8c authored by Trigger Huang's avatar Trigger Huang Committed by Alex Deucher
Browse files

drm/amdgpu: Use FW addr returned by PSP for VF MM 



One Vega10 SR-IOV VF, the FW address returned by PSP should be
set into the init table, while not the original BO mc address.
otherwise, UVD and VCE IB test will fail under Vega10 SR-IOV

reference:
	commit bfcea520 ("drm/amdgpu:change VEGA booting with firmware loaded by PSP")
	commit aa5873dc ("drm/amdgpu: Change VCE booting with firmware loaded by PSP")

Signed-off-by: default avatarTrigger Huang <Trigger.Huang@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 570c91d5

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

+10 −6
Original line number Diff line number Diff line
@@ -787,10 +787,13 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) 
							   0xFFFFFFFF, 0x00000004);

			/* mc resume*/

			if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

							    lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));

				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

							    upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));

				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,

							mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

							adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo);

				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,

							mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

							adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi);

				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);

				offset = 0;

			} else {

				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
@@ -798,10 +801,11 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) 
				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),

							    upper_32_bits(adev->uvd.inst[i].gpu_addr));

				offset = size;

				MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),

							AMDGPU_UVD_FIRMWARE_OFFSET >> 3);



			}



			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),

						    AMDGPU_UVD_FIRMWARE_OFFSET >> 3);

			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);



			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

+11 −6
Original line number Diff line number Diff line
@@ -244,13 +244,18 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev) 
		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);

		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);



		offset = AMDGPU_VCE_FIRMWARE_OFFSET;

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

			uint32_t low = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_lo;

			uint32_t hi = adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].tmr_mc_addr_hi;

			uint64_t tmr_mc_addr = (uint64_t)(hi) << 32 | low;



			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

						mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),

						adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);

						mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), tmr_mc_addr >> 8);

			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

						mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),

						(adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff);

						(tmr_mc_addr >> 40) & 0xff);

			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);

		} else {

			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

						mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
@@ -258,6 +263,9 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev) 
			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

						mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),

						(adev->vce.gpu_addr >> 40) & 0xff);

			MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),

						offset & ~0x0f000000);



		}

		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

						mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
@@ -272,10 +280,7 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev) 
						mmVCE_LMI_VCPU_CACHE_64BIT_BAR2),

						(adev->vce.gpu_addr >> 40) & 0xff);



		offset = AMDGPU_VCE_FIRMWARE_OFFSET;

		size = VCE_V4_0_FW_SIZE;

		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),

					offset & ~0x0f000000);

		MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);



		offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset + size : 0;

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