Commit 98cad2de authored by Trigger Huang's avatar Trigger Huang Committed by Alex Deucher
Browse files

drm/amdgpu: Skip setting some regs under Vega10 VF 



For Vega10 SR-IOV VF, skip setting some regs due to:
1, host will program them
2, avoid VF register programming violations

Signed-off-by: default avatarTrigger Huang <Trigger.Huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7bd87769

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+8 −6
Original line number Diff line number Diff line
@@ -308,12 +308,14 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 
{

	switch (adev->asic_type) {

	case CHIP_VEGA10:

		if (!amdgpu_virt_support_skip_setting(adev)) {

			soc15_program_register_sequence(adev,

							 golden_settings_gc_9_0,

							 ARRAY_SIZE(golden_settings_gc_9_0));

			soc15_program_register_sequence(adev,

							 golden_settings_gc_9_0_vg10,

							 ARRAY_SIZE(golden_settings_gc_9_0_vg10));

		}

		break;

	case CHIP_VEGA12:

		soc15_program_register_sequence(adev,

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+3 −0
Original line number Diff line number Diff line
@@ -1097,6 +1097,9 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 


	switch (adev->asic_type) {

	case CHIP_VEGA10:

		if (amdgpu_virt_support_skip_setting(adev))

			break;

		/* fall through */

	case CHIP_VEGA20:

		soc15_program_register_sequence(adev,

						golden_settings_mmhub_1_0_0,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+20 −5
Original line number Diff line number Diff line
@@ -111,6 +111,9 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 
		WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

			     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



	if (amdgpu_virt_support_skip_setting(adev))

		return;



	/* Set default page address. */

	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +

		adev->vm_manager.vram_base_offset;
@@ -156,6 +159,9 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
{

	uint32_t tmp;



	if (amdgpu_virt_support_skip_setting(adev))

		return;



	/* Setup L2 cache */

	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -202,6 +208,9 @@ static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 


static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)

{

	if (amdgpu_virt_support_skip_setting(adev))

		return;



	WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,

		     0XFFFFFFFF);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
@@ -338,12 +347,14 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) 
				0);

	WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);



	if (!amdgpu_virt_support_skip_setting(adev)) {

		/* Setup L2 cache */

		tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);

		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

		WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);

		WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);

	}

}



/**

 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
@@ -354,6 +365,10 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) 
void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)

{

	u32 tmp;



	if (amdgpu_virt_support_skip_setting(adev))

		return;



	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

			RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+8 −6
Original line number Diff line number Diff line
@@ -210,12 +210,14 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 
{

	switch (adev->asic_type) {

	case CHIP_VEGA10:

		if (!amdgpu_virt_support_skip_setting(adev)) {

			soc15_program_register_sequence(adev,

							 golden_settings_sdma_4,

							 ARRAY_SIZE(golden_settings_sdma_4));

			soc15_program_register_sequence(adev,

							 golden_settings_sdma_vg10,

							 ARRAY_SIZE(golden_settings_sdma_vg10));

		}

		break;

	case CHIP_VEGA12:

		soc15_program_register_sequence(adev,

drivers/gpu/drm/amd/amdgpu/soc15.c

+11 −5
Original line number Diff line number Diff line
@@ -1024,12 +1024,18 @@ static void soc15_doorbell_range_init(struct amdgpu_device *adev) 
	int i;

	struct amdgpu_ring *ring;



	/*  Two reasons to skip

	*		1, Host driver already programmed them

	*		2, To avoid registers program violations in SR-IOV

	*/

	if (!amdgpu_virt_support_skip_setting(adev)) {

		for (i = 0; i < adev->sdma.num_instances; i++) {

			ring = &adev->sdma.instance[i].ring;

			adev->nbio_funcs->sdma_doorbell_range(adev, i,

				ring->use_doorbell, ring->doorbell_index,

				adev->doorbell_index.sdma_doorbell_range);

		}

	}



	adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,

						adev->irq.ih.doorbell_index);

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