Commit 7bd87769 authored by Trigger Huang's avatar Trigger Huang Committed by Alex Deucher
Browse files

drm/amdgpu: Support PSP VMR ring for Vega10 VF 



Add VMR ring support for Vega10 SR-IOV VF if PSP supported

Signed-off-by: default avatarTrigger Huang <Trigger.Huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 470b4250

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

+99 −32
Original line number Diff line number Diff line
@@ -50,6 +50,10 @@ MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); 


static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554};



static bool psp_v3_1_support_vmr_ring(struct psp_context *psp);

static int psp_v3_1_ring_stop(struct psp_context *psp,

			      enum psp_ring_type ring_type);



static int psp_v3_1_init_microcode(struct psp_context *psp)

{

	struct amdgpu_device *adev = psp->adev;
@@ -296,6 +300,34 @@ static int psp_v3_1_ring_create(struct psp_context *psp, 


	psp_v3_1_reroute_ih(psp);



	if (psp_v3_1_support_vmr_ring(psp)) {

		ret = psp_v3_1_ring_stop(psp, ring_type);

		if (ret) {

			DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");

			return ret;

		}



		/* Write low address of the ring to C2PMSG_102 */

		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);

		/* Write high address of the ring to C2PMSG_103 */

		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);

		/* No size initialization for sriov  */

		/* Write the ring initialization command to C2PMSG_101 */

		psp_ring_reg = ring_type;

		psp_ring_reg = psp_ring_reg << 16;

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);



		/* there might be hardware handshake issue which needs delay */

		mdelay(20);



		/* Wait for response flag (bit 31) in C2PMSG_101 */

		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,

					mmMP0_SMN_C2PMSG_101), 0x80000000,

					0x8000FFFF, false);

	} else {



		/* Write low address of the ring to C2PMSG_69 */

		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
@@ -310,13 +342,15 @@ static int psp_v3_1_ring_create(struct psp_context *psp, 
		psp_ring_reg = psp_ring_reg << 16;

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);



	/* there might be handshake issue with hardware which needs delay */

		/* there might be hardware handshake issue which needs delay */

		mdelay(20);



		/* Wait for response flag (bit 31) in C2PMSG_64 */

	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

			   0x80000000, 0x8000FFFF, false);

		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,

					mmMP0_SMN_C2PMSG_64), 0x80000000,

					0x8000FFFF, false);



	}

	return ret;

}
@@ -327,16 +361,31 @@ static int psp_v3_1_ring_stop(struct psp_context *psp, 
	unsigned int psp_ring_reg = 0;

	struct amdgpu_device *adev = psp->adev;



	if (psp_v3_1_support_vmr_ring(psp)) {

		/* Write the Destroy GPCOM ring command to C2PMSG_101 */

		psp_ring_reg = GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING;

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);



		/* there might be handshake issue which needs delay */

		mdelay(20);



		/* Wait for response flag (bit 31) in C2PMSG_101 */

		ret = psp_wait_for(psp,

				SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),

				0x80000000, 0x80000000, false);

	} else {

		/* Write the ring destroy command to C2PMSG_64 */

		psp_ring_reg = 3 << 16;

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);



	/* there might be handshake issue with hardware which needs delay */

		/* there might be handshake issue which needs delay */

		mdelay(20);



		/* Wait for response flag (bit 31) in C2PMSG_64 */

	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

		ret = psp_wait_for(psp,

				SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),

				0x80000000, 0x80000000, false);

	}



	return ret;

}
@@ -375,6 +424,9 @@ static int psp_v3_1_cmd_submit(struct psp_context *psp, 
	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;



	/* KM (GPCOM) prepare write pointer */

	if (psp_v3_1_support_vmr_ring(psp))

		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);

	else

		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);



	/* Update KM RB frame pointer to new frame */
@@ -404,6 +456,12 @@ static int psp_v3_1_cmd_submit(struct psp_context *psp, 


	/* Update the write Pointer in DWORDs */

	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;

	if (psp_v3_1_support_vmr_ring(psp)) {

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);

		/* send interrupt to PSP for SRIOV ring write pointer update */

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,

					GFX_CTRL_CMD_ID_CONSUME_CMD);

	} else

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);



	return 0;
@@ -574,6 +632,14 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp) 
	return 0;

}



static bool psp_v3_1_support_vmr_ring(struct psp_context *psp)

{

	if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version >= 0x80455)

		return true;



	return false;

}



static const struct psp_funcs psp_v3_1_funcs = {

	.init_microcode = psp_v3_1_init_microcode,

	.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
@@ -586,6 +652,7 @@ static const struct psp_funcs psp_v3_1_funcs = { 
	.compare_sram_data = psp_v3_1_compare_sram_data,

	.smu_reload_quirk = psp_v3_1_smu_reload_quirk,

	.mode1_reset = psp_v3_1_mode1_reset,

	.support_vmr_ring = psp_v3_1_support_vmr_ring,

};



void psp_v3_1_set_psp_funcs(struct psp_context *psp)

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