Commit 987106e5 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-https', 'clk-renesas', 'clk-kconfig', 'clk-amlogic' and 'clk-imx' into clk-next 

* clk-https:
  Replace HTTP links with HTTPS ones: Common CLK framework

* clk-renesas:
  clk: renesas: cpg-mssr: Add r8a774e1 support
  dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1
  clk: renesas: Add r8a774e1 CPG Core Clock Definitions
  dt-bindings: power: Add r8a774e1 SYSC power domain definitions
  clk: renesas: rzg2: Mark RWDT clocks as critical
  clk: renesas: rcar-gen3: Mark RWDT clocks as critical
  clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot
  dt-bindings: clock: renesas: cpg: Convert to json-schema

* clk-kconfig:
  clk: hsdk: Fix bad dependency on IOMEM
  clk: Specify IOMEM dependency for HSDK pll driver
  clk: Drop duplicate selection in Kconfig
  clk: AST2600: Add mux for EMMC clock
  clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER

* clk-amlogic:
  clk: meson: meson8b: add the vclk2_en gate clock
  clk: meson: meson8b: add the vclk_en gate clock
  clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
  clk: meson: g12a: Add support for NNA CLK source clocks
  dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs

* clk-imx:
  clk: imx: vf610: add CAAM clock
  clk: imx8mp: add mu root clk
parents c63e2a7a 5f1d8970 210f7240 bd8548d0 bfd35bf9 22b1408b

Documentation/devicetree/bindings/clock/clock-bindings.txt

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Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ specifier is an array of zero, one or more cells identifying the clock 
output on a device.  The length of a clock specifier is defined by the

value of a #clock-cells property in the clock provider node.



[1] http://patchwork.ozlabs.org/patch/31551/

[1] https://patchwork.ozlabs.org/patch/31551/



==Clock providers==

Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas Clock Pulse Generator (CPG)



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description:

  The Clock Pulse Generator (CPG) generates core clocks for the SoC.  It

  includes PLLs, and fixed and variable ratio dividers.



  The CPG may also provide a Clock Domain for SoC devices, in combination with

  the CPG Module Stop (MSTP) Clocks.



properties:

  compatible:

    oneOf:

      - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6

      - const: renesas,r8a7740-cpg-clocks # R-Mobile A1

      - const: renesas,r8a7778-cpg-clocks # R-Car M1

      - const: renesas,r8a7779-cpg-clocks # R-Car H1

      - items:

        - enum:

            - renesas,r7s72100-cpg-clocks # RZ/A1H

        - const: renesas,rz-cpg-clocks    # RZ/A1

      - const: renesas,sh73a0-cpg-clocks  # SH-Mobile AG5



  reg:

    maxItems: 1



  clocks: true



  '#clock-cells':

    const: 1



  clock-output-names: true



  renesas,mode:

    description: Board-specific settings of the MD_CK* bits on R-Mobile A1

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 0

    maximum: 7



  '#power-domain-cells':

    const: 0



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - clock-output-names



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: renesas,r8a73a4-cpg-clocks

    then:

      properties:

        clocks:

          items:

            - description: extal1

            - description: extal2



        clock-output-names:

          items:

            - const: main

            - const: pll0

            - const: pll1

            - const: pll2

            - const: pll2s

            - const: pll2h

            - const: z

            - const: z2

            - const: i

            - const: m3

            - const: b

            - const: m1

            - const: m2

            - const: zx

            - const: zs

            - const: hp



  - if:

      properties:

        compatible:

          contains:

            const: renesas,r8a7740-cpg-clocks

    then:

      properties:

        clocks:

          items:

            - description: extal1

            - description: extal2

            - description: extalr



        clock-output-names:

          items:

            - const: system

            - const: pllc0

            - const: pllc1

            - const: pllc2

            - const: r

            - const: usb24s

            - const: i

            - const: zg

            - const: b

            - const: m1

            - const: hp

            - const: hpp

            - const: usbp

            - const: s

            - const: zb

            - const: m3

            - const: cp



      required:

        - renesas,mode



  - if:

      properties:

        compatible:

          contains:

            const: renesas,r8a7778-cpg-clocks

    then:

      properties:

        clocks:

          maxItems: 1



        clock-output-names:

          items:

            - const: plla

            - const: pllb

            - const: b

            - const: out

            - const: p

            - const: s

            - const: s1



  - if:

      properties:

        compatible:

          contains:

            const: renesas,r8a7779-cpg-clocks

    then:

      properties:

        clocks:

          maxItems: 1



        clock-output-names:

          items:

            - const: plla

            - const: z

            - const: zs

            - const: s

            - const: s1

            - const: p

            - const: b

            - const: out



  - if:

      properties:

        compatible:

          contains:

            const: renesas,r7s72100-cpg-clocks

    then:

      properties:

        clocks:

          items:

            - description: extal1

            - description: usb_x1



        clock-output-names:

          items:

            - const: pll

            - const: i

            - const: g



  - if:

      properties:

        compatible:

          contains:

            const: renesas,sh73a0-cpg-clocks

    then:

      properties:

        clocks:

          items:

            - description: extal1

            - description: extal2



        clock-output-names:

          items:

            - const: main

            - const: pll0

            - const: pll1

            - const: pll2

            - const: pll3

            - const: dsi0phy

            - const: dsi1phy

            - const: zg

            - const: m3

            - const: b

            - const: m1

            - const: m2

            - const: z

            - const: zx

            - const: hp



  - if:

      properties:

        compatible:

          contains:

            enum:

              - renesas,r8a7778-cpg-clocks

              - renesas,r8a7779-cpg-clocks

              - renesas,rz-cpg-clocks

    then:

      required:

        - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/r8a7740-clock.h>

    cpg_clocks: cpg_clocks@e6150000 {

            compatible = "renesas,r8a7740-cpg-clocks";

            reg = <0xe6150000 0x10000>;

            clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;

            #clock-cells = <1>;

            clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",

                                 "usb24s", "i", "zg", "b", "m1", "hp", "hpp",

                                 "usbp", "s", "zb", "m3", "cp";

            renesas,mode = <0x05>;

    };

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

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@@ -33,6 +33,7 @@ properties: 
      - renesas,r8a774a1-cpg-mssr # RZ/G2M

      - renesas,r8a774b1-cpg-mssr # RZ/G2N

      - renesas,r8a774c0-cpg-mssr # RZ/G2E

      - renesas,r8a774e1-cpg-mssr # RZ/G2H

      - renesas,r8a7790-cpg-mssr  # R-Car H2

      - renesas,r8a7791-cpg-mssr  # R-Car M2-W

      - renesas,r8a7792-cpg-mssr  # R-Car V2H

Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt

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* Renesas R8A73A4 Clock Pulse Generator (CPG)



The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs

and several fixed ratio dividers.



Required Properties:



  - compatible: Must be "renesas,r8a73a4-cpg-clocks"



  - reg: Base address and length of the memory resource used by the CPG



  - clocks: Reference to the parent clocks ("extal1" and "extal2")



  - #clock-cells: Must be 1



  - clock-output-names: The names of the clocks. Supported clocks are "main",

    "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",

    "m1", "m2", "zx", "zs", and "hp".





Example

-------



        cpg_clocks: cpg_clocks@e6150000 {

                compatible = "renesas,r8a73a4-cpg-clocks";

                reg = <0 0xe6150000 0 0x10000>;

                clocks = <&extal1_clk>, <&extal2_clk>;

                #clock-cells = <1>;

                clock-output-names = "main", "pll0", "pll1", "pll2",

                                     "pll2s", "pll2h", "z", "z2",

                                     "i", "m3", "b", "m1", "m2",

                                     "zx", "zs", "hp";

        };

Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt

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Original line number Diff line number Diff line 
These bindings should be considered EXPERIMENTAL for now.



* Renesas R8A7740  Clock Pulse Generator (CPG)



The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs

and several fixed ratio and variable ratio dividers.



Required Properties:



  - compatible: Must be "renesas,r8a7740-cpg-clocks"



  - reg: Base address and length of the memory resource used by the CPG



  - clocks: Reference to the three parent clocks

  - #clock-cells: Must be 1

  - clock-output-names: The names of the clocks. Supported clocks are

    "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",

    "m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".



  - renesas,mode: board-specific settings of the MD_CK* bits





Example

-------



cpg_clocks: cpg_clocks@e6150000 {

        compatible = "renesas,r8a7740-cpg-clocks";

        reg = <0xe6150000 0x10000>;

        clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;

        #clock-cells = <1>;

        clock-output-names = "system", "pllc0", "pllc1",

                             "pllc2", "r",

                             "usb24s",

                             "i", "zg", "b", "m1", "hp",

                             "hpp", "usbp", "s", "zb", "m3",

                             "cp";

};



&cpg_clocks {

	renesas,mode = <0x05>;

};

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