Commit bfd35bf9 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v5.9-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk driver updates from Jerome Brunet:

 - g12: add neural network accelerator clock sources
 - meson8: remove critical flag for main PLL divider
 - meson8: add video decoder clock gates

* tag 'clk-meson-v5.9-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: add the vclk2_en gate clock
  clk: meson: meson8b: add the vclk_en gate clock
  clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
  clk: meson: g12a: Add support for NNA CLK source clocks
  dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
parents b3a9e3b9 2568528f

drivers/clk/meson/g12a.c

+119 −0
Original line number Diff line number Diff line
@@ -3981,6 +3981,113 @@ static struct clk_regmap g12a_spicc1_sclk = { 
	},

};



/* Neural Network Accelerator source clock */



static const struct clk_parent_data nna_clk_parent_data[] = {

	{ .fw_name = "xtal", },

	{ .hw = &g12a_gp0_pll.hw, },

	{ .hw = &g12a_hifi_pll.hw, },

	{ .hw = &g12a_fclk_div2p5.hw, },

	{ .hw = &g12a_fclk_div3.hw, },

	{ .hw = &g12a_fclk_div4.hw, },

	{ .hw = &g12a_fclk_div5.hw, },

	{ .hw = &g12a_fclk_div7.hw },

};



static struct clk_regmap sm1_nna_axi_clk_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_NNA_CLK_CNTL,

		.mask = 7,

		.shift = 9,

	},

	.hw.init = &(struct clk_init_data){

		.name = "nna_axi_clk_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_data = nna_clk_parent_data,

		.num_parents = ARRAY_SIZE(nna_clk_parent_data),

	},

};



static struct clk_regmap sm1_nna_axi_clk_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_NNA_CLK_CNTL,

		.shift = 0,

		.width = 7,

	},

	.hw.init = &(struct clk_init_data){

		.name = "nna_axi_clk_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&sm1_nna_axi_clk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap sm1_nna_axi_clk = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_NNA_CLK_CNTL,

		.bit_idx = 8,

	},

	.hw.init = &(struct clk_init_data){

		.name = "nna_axi_clk",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&sm1_nna_axi_clk_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap sm1_nna_core_clk_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_NNA_CLK_CNTL,

		.mask = 7,

		.shift = 25,

	},

	.hw.init = &(struct clk_init_data){

		.name = "nna_core_clk_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_data = nna_clk_parent_data,

		.num_parents = ARRAY_SIZE(nna_clk_parent_data),

	},

};



static struct clk_regmap sm1_nna_core_clk_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_NNA_CLK_CNTL,

		.shift = 16,

		.width = 7,

	},

	.hw.init = &(struct clk_init_data){

		.name = "nna_core_clk_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&sm1_nna_core_clk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap sm1_nna_core_clk = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_NNA_CLK_CNTL,

		.bit_idx = 24,

	},

	.hw.init = &(struct clk_init_data){

		.name = "nna_core_clk",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&sm1_nna_core_clk_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



#define MESON_GATE(_name, _reg, _bit) \

	MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
@@ -4779,6 +4886,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { 
		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,

		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,

		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,

		[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,

		[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,

		[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,

		[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,

		[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,

		[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,
@@ -5020,6 +5133,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { 
	&g12a_spicc1_sclk_sel,

	&g12a_spicc1_sclk_div,

	&g12a_spicc1_sclk,

	&sm1_nna_axi_clk_sel,

	&sm1_nna_axi_clk_div,

	&sm1_nna_axi_clk,

	&sm1_nna_core_clk_sel,

	&sm1_nna_core_clk_div,

	&sm1_nna_core_clk,

};



static const struct reg_sequence g12a_init_regs[] = {

drivers/clk/meson/g12a.h

+6 −1
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ 
#define HHI_MALI_CLK_CNTL		0x1b0

#define HHI_VPU_CLKC_CNTL		0x1b4

#define HHI_VPU_CLK_CNTL		0x1bC

#define HHI_NNA_CLK_CNTL		0x1C8

#define HHI_HDMI_CLK_CNTL		0x1CC

#define HHI_VDEC_CLK_CNTL		0x1E0

#define HHI_VDEC2_CLK_CNTL		0x1E4
@@ -259,8 +260,12 @@ 
#define CLKID_SPICC0_SCLK_DIV			257

#define CLKID_SPICC1_SCLK_SEL			259

#define CLKID_SPICC1_SCLK_DIV			260

#define CLKID_NNA_AXI_CLK_SEL			262

#define CLKID_NNA_AXI_CLK_DIV			263

#define CLKID_NNA_CORE_CLK_SEL			265

#define CLKID_NNA_CORE_CLK_DIV			266



#define NR_CLKS					262

#define NR_CLKS					268



/* include the CLKIDs that have been made part of the DT binding */

#include <dt-bindings/clock/g12a-clkc.h>

drivers/clk/meson/meson8b.c

+50 −17
Original line number Diff line number Diff line
@@ -293,13 +293,6 @@ static struct clk_regmap meson8b_fclk_div2 = { 
			&meson8b_fclk_div2_div.hw

		},

		.num_parents = 1,

		/*

		 * FIXME: Ethernet with a RGMII PHYs is not working if

		 * fclk_div2 is disabled. it is currently unclear why this

		 * is. keep it enabled until the Ethernet driver knows how

		 * to manage this clock.

		 */

		.flags = CLK_IS_CRITICAL,

	},

};
@@ -1211,6 +1204,22 @@ static struct clk_regmap meson8b_vclk_in_en = { 
	},

};



static struct clk_regmap meson8b_vclk_en = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_VID_CLK_CNTL,

		.bit_idx = 19,

	},

	.hw.init = &(struct clk_init_data){

		.name = "vclk_en",

		.ops = &clk_regmap_gate_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk_in_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap meson8b_vclk_div1_gate = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_VID_CLK_CNTL,
@@ -1220,7 +1229,7 @@ static struct clk_regmap meson8b_vclk_div1_gate = { 
		.name = "vclk_div1_en",

		.ops = &clk_regmap_gate_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk_in_en.hw

			&meson8b_vclk_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,
@@ -1234,7 +1243,7 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = { 
		.name = "vclk_div2",

		.ops = &clk_fixed_factor_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk_in_en.hw

			&meson8b_vclk_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,
@@ -1264,7 +1273,7 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = { 
		.name = "vclk_div4",

		.ops = &clk_fixed_factor_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk_in_en.hw

			&meson8b_vclk_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,
@@ -1294,7 +1303,7 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = { 
		.name = "vclk_div6",

		.ops = &clk_fixed_factor_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk_in_en.hw

			&meson8b_vclk_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,
@@ -1324,7 +1333,7 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = { 
		.name = "vclk_div12",

		.ops = &clk_fixed_factor_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk_in_en.hw

			&meson8b_vclk_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,
@@ -1378,6 +1387,22 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = { 
	},

};



static struct clk_regmap meson8b_vclk2_clk_en = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_VIID_CLK_DIV,

		.bit_idx = 19,

	},

	.hw.init = &(struct clk_init_data){

		.name = "vclk2_en",

		.ops = &clk_regmap_gate_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk2_clk_in_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap meson8b_vclk2_div1_gate = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_VIID_CLK_DIV,
@@ -1387,7 +1412,7 @@ static struct clk_regmap meson8b_vclk2_div1_gate = { 
		.name = "vclk2_div1_en",

		.ops = &clk_regmap_gate_ro_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk2_clk_in_en.hw

			&meson8b_vclk2_clk_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,
@@ -1401,7 +1426,7 @@ static struct clk_fixed_factor meson8b_vclk2_div2_div = { 
		.name = "vclk2_div2",

		.ops = &clk_fixed_factor_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk2_clk_in_en.hw

			&meson8b_vclk2_clk_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,
@@ -1431,7 +1456,7 @@ static struct clk_fixed_factor meson8b_vclk2_div4_div = { 
		.name = "vclk2_div4",

		.ops = &clk_fixed_factor_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk2_clk_in_en.hw

			&meson8b_vclk2_clk_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,
@@ -1461,7 +1486,7 @@ static struct clk_fixed_factor meson8b_vclk2_div6_div = { 
		.name = "vclk2_div6",

		.ops = &clk_fixed_factor_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk2_clk_in_en.hw

			&meson8b_vclk2_clk_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,
@@ -1491,7 +1516,7 @@ static struct clk_fixed_factor meson8b_vclk2_div12_div = { 
		.name = "vclk2_div12",

		.ops = &clk_fixed_factor_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8b_vclk2_clk_in_en.hw

			&meson8b_vclk2_clk_en.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,
@@ -2827,6 +2852,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = { 
		[CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,

		[CLKID_VCLK_IN_SEL]	    = &meson8b_vclk_in_sel.hw,

		[CLKID_VCLK_IN_EN]	    = &meson8b_vclk_in_en.hw,

		[CLKID_VCLK_EN]		    = &meson8b_vclk_en.hw,

		[CLKID_VCLK_DIV1]	    = &meson8b_vclk_div1_gate.hw,

		[CLKID_VCLK_DIV2_DIV]	    = &meson8b_vclk_div2_div.hw,

		[CLKID_VCLK_DIV2]	    = &meson8b_vclk_div2_div_gate.hw,
@@ -2838,6 +2864,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = { 
		[CLKID_VCLK_DIV12]	    = &meson8b_vclk_div12_div_gate.hw,

		[CLKID_VCLK2_IN_SEL]	    = &meson8b_vclk2_in_sel.hw,

		[CLKID_VCLK2_IN_EN]	    = &meson8b_vclk2_clk_in_en.hw,

		[CLKID_VCLK2_EN]	    = &meson8b_vclk2_clk_en.hw,

		[CLKID_VCLK2_DIV1]	    = &meson8b_vclk2_div1_gate.hw,

		[CLKID_VCLK2_DIV2_DIV]	    = &meson8b_vclk2_div2_div.hw,

		[CLKID_VCLK2_DIV2]	    = &meson8b_vclk2_div2_div_gate.hw,
@@ -3032,6 +3059,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { 
		[CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,

		[CLKID_VCLK_IN_SEL]	    = &meson8b_vclk_in_sel.hw,

		[CLKID_VCLK_IN_EN]	    = &meson8b_vclk_in_en.hw,

		[CLKID_VCLK_EN]		    = &meson8b_vclk_en.hw,

		[CLKID_VCLK_DIV1]	    = &meson8b_vclk_div1_gate.hw,

		[CLKID_VCLK_DIV2_DIV]	    = &meson8b_vclk_div2_div.hw,

		[CLKID_VCLK_DIV2]	    = &meson8b_vclk_div2_div_gate.hw,
@@ -3043,6 +3071,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { 
		[CLKID_VCLK_DIV12]	    = &meson8b_vclk_div12_div_gate.hw,

		[CLKID_VCLK2_IN_SEL]	    = &meson8b_vclk2_in_sel.hw,

		[CLKID_VCLK2_IN_EN]	    = &meson8b_vclk2_clk_in_en.hw,

		[CLKID_VCLK2_EN]	    = &meson8b_vclk2_clk_en.hw,

		[CLKID_VCLK2_DIV1]	    = &meson8b_vclk2_div1_gate.hw,

		[CLKID_VCLK2_DIV2_DIV]	    = &meson8b_vclk2_div2_div.hw,

		[CLKID_VCLK2_DIV2]	    = &meson8b_vclk2_div2_div_gate.hw,
@@ -3248,6 +3277,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = { 
		[CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,

		[CLKID_VCLK_IN_SEL]	    = &meson8b_vclk_in_sel.hw,

		[CLKID_VCLK_IN_EN]	    = &meson8b_vclk_in_en.hw,

		[CLKID_VCLK_EN]		    = &meson8b_vclk_en.hw,

		[CLKID_VCLK_DIV1]	    = &meson8b_vclk_div1_gate.hw,

		[CLKID_VCLK_DIV2_DIV]	    = &meson8b_vclk_div2_div.hw,

		[CLKID_VCLK_DIV2]	    = &meson8b_vclk_div2_div_gate.hw,
@@ -3259,6 +3289,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = { 
		[CLKID_VCLK_DIV12]	    = &meson8b_vclk_div12_div_gate.hw,

		[CLKID_VCLK2_IN_SEL]	    = &meson8b_vclk2_in_sel.hw,

		[CLKID_VCLK2_IN_EN]	    = &meson8b_vclk2_clk_in_en.hw,

		[CLKID_VCLK2_EN]	    = &meson8b_vclk2_clk_en.hw,

		[CLKID_VCLK2_DIV1]	    = &meson8b_vclk2_div1_gate.hw,

		[CLKID_VCLK2_DIV2_DIV]	    = &meson8b_vclk2_div2_div.hw,

		[CLKID_VCLK2_DIV2]	    = &meson8b_vclk2_div2_div_gate.hw,
@@ -3450,6 +3481,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { 
	&meson8b_vid_pll_final_div,

	&meson8b_vclk_in_sel,

	&meson8b_vclk_in_en,

	&meson8b_vclk_en,

	&meson8b_vclk_div1_gate,

	&meson8b_vclk_div2_div_gate,

	&meson8b_vclk_div4_div_gate,
@@ -3457,6 +3489,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { 
	&meson8b_vclk_div12_div_gate,

	&meson8b_vclk2_in_sel,

	&meson8b_vclk2_clk_in_en,

	&meson8b_vclk2_clk_en,

	&meson8b_vclk2_div1_gate,

	&meson8b_vclk2_div2_div_gate,

	&meson8b_vclk2_div4_div_gate,

drivers/clk/meson/meson8b.h

+3 −1
Original line number Diff line number Diff line
@@ -180,8 +180,10 @@ 
#define CLKID_CTS_AMCLK_DIV	208

#define CLKID_CTS_MCLK_I958_SEL	210

#define CLKID_CTS_MCLK_I958_DIV	211

#define CLKID_VCLK_EN		214

#define CLKID_VCLK2_EN		215



#define CLK_NR_CLKS		214

#define CLK_NR_CLKS		216



/*

 * include the CLKID and RESETID that have

include/dt-bindings/clock/g12a-clkc.h

+2 −0
Original line number Diff line number Diff line
@@ -145,5 +145,7 @@ 
#define CLKID_CPU3_CLK				255

#define CLKID_SPICC0_SCLK			258

#define CLKID_SPICC1_SCLK			261

#define CLKID_NNA_AXI_CLK			264

#define CLKID_NNA_CORE_CLK			267



#endif /* __G12A_CLKC_H */

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