Commit 97f67898 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Paul Walmsley
Browse files

OMAP4: DPLL: Add dpll api to control GATE_CTRL 



On OMAP4, the dpll post divider outputs (MX outputs)
along with clockout_x2 output provide a way to allow/deny
hardware level autogating.
Allowing autoidle would mean that the hw would autogate
this clock when there is no dependency for it.
Denying idle would mean that this clock output will be
forced to stay enabled.

Add dpll api's to read/allow/deny idle control
for these dpll mx postdividers.

NOTE: The gatectrl bit set to 0 allows gatectrl,
and the bit set to 1 denies gatectrl.

Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: moved OMAP4-specific DPLL control code to
 mach-omap2/dpll44xx.c; added some documentation for CLOCK_CLKOUTX2]
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent b80b956d

arch/arm/mach-omap2/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -123,7 +123,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ 
					   clock3517.o clock36xx.o \

					   dpll3xxx.o clock3xxx_data.o

obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) clock44xx_data.o \

					   dpll3xxx.o

					   dpll3xxx.o dpll44xx.o



# OMAP2 clock rate set data (old "OPP" data)

obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o

arch/arm/mach-omap2/clock.h

+3 −0
Original line number Diff line number Diff line
@@ -65,6 +65,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk); 
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);

int omap3_noncore_dpll_enable(struct clk *clk);

void omap3_noncore_dpll_disable(struct clk *clk);

int omap4_dpllmx_gatectrl_read(struct clk *clk);

void omap4_dpllmx_allow_gatectrl(struct clk *clk);

void omap4_dpllmx_deny_gatectrl(struct clk *clk);



#ifdef CONFIG_OMAP_RESET_CLOCKS

void omap2_clk_disable_unused(struct clk *clk);

arch/arm/mach-omap2/dpll44xx.c

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+78 −0
Original line number Diff line number Diff line 
/*

 * OMAP4-specific DPLL control functions

 *

 * Copyright (C) 2011 Texas Instruments, Inc.

 * Rajendra Nayak

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#include <linux/kernel.h>

#include <linux/errno.h>

#include <linux/clk.h>

#include <linux/io.h>

#include <linux/bitops.h>



#include <plat/cpu.h>

#include <plat/clock.h>



#include "clock.h"

#include "cm-regbits-44xx.h"



/* Supported only on OMAP4 */

int omap4_dpllmx_gatectrl_read(struct clk *clk)

{

	u32 v;

	u32 mask;



	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())

		return -EINVAL;



	mask = clk->flags & CLOCK_CLKOUTX2 ?

			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :

			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;



	v = __raw_readl(clk->clksel_reg);

	v &= mask;

	v >>= __ffs(mask);



	return v;

}



void omap4_dpllmx_allow_gatectrl(struct clk *clk)

{

	u32 v;

	u32 mask;



	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())

		return;



	mask = clk->flags & CLOCK_CLKOUTX2 ?

			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :

			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;



	v = __raw_readl(clk->clksel_reg);

	/* Clear the bit to allow gatectrl */

	v &= ~mask;

	__raw_writel(v, clk->clksel_reg);

}



void omap4_dpllmx_deny_gatectrl(struct clk *clk)

{

	u32 v;

	u32 mask;



	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())

		return;



	mask = clk->flags & CLOCK_CLKOUTX2 ?

			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :

			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;



	v = __raw_readl(clk->clksel_reg);

	/* Set the bit to deny gatectrl */

	v |= mask;

	__raw_writel(v, clk->clksel_reg);

}

arch/arm/plat-omap/include/plat/clock.h

+13 −1
Original line number Diff line number Diff line
@@ -176,12 +176,24 @@ struct dpll_data { 


#endif



/* struct clk.flags possibilities */

/*

 * struct clk.flags possibilities

 *

 * XXX document the rest of the clock flags here

 *

 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL

 *     bits share the same register.  This flag allows the

 *     omap4_dpllmx*() code to determine which GATE_CTRL bit field

 *     should be used.  This is a temporary solution - a better approach

 *     would be to associate clock type-specific data with the clock,

 *     similar to the struct dpll_data approach.

 */

#define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */

#define CLOCK_IDLE_CONTROL	(1 << 1)

#define CLOCK_NO_IDLE_PARENT	(1 << 2)

#define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */

#define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */

#define CLOCK_CLKOUTX2		(1 << 5)



/**

 * struct clk - OMAP struct clk

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