OMAP2+: clock: autoidle as many clocks as possible if CONFIG_OMAP_RESET_CLOCKS (b80b956d) · Commits · 戴 / test

Attempt to enable autoidle for as many clocks as possible in the OMAP2+-common CONFIG_OMAP_RESET_CLOCKS code. Currently, this only enables DPLL autoidle for OMAP3/4 DPLLs; but future patches will enable autoidle for other clocks and the OMAP2 DPLL/APLLs. In the long run, we should probably get rid of CONFIG_OMAP_RESET_CLOCKS, and unconditionally run the code that it selects. Otherwise, the state of the clock tree won't match the hardware state - this could result in clocks being enabled or disabled unpredictably. Based on a patch by Rajendra Nayak <rnayak@ti.com> that did this in the pm34xx.c/pm44xx.c code. Signed-off-by:

Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>

arch/arm/mach-omap2/pm34xx.c

+0 −17

Original line number	Diff line number	Diff line
		@@ -813,23 +813,6 @@ static void __init prcm_setup_regs(void)

		omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);

		/*
		* Set all plls to autoidle. This is needed until autoidle is
		* enabled by clockfw
		*/
		omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
		OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
		omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
		MPU_MOD,
		CM_AUTOIDLE2);
		omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) \|
		(1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
		PLL_MOD,
		CM_AUTOIDLE);
		omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
		PLL_MOD,
		CM_AUTOIDLE2);

		/*
		* Enable control of expternal oscillator through
		* sys_clkreq. In the long run clock framework should

arch/arm/plat-omap/clock.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -446,6 +446,7 @@ static int __init clk_disable_unused(void)
		return 0;
		}
		late_initcall(clk_disable_unused);
		late_initcall(omap_clk_enable_autoidle_all);
		#endif

		int __init clk_init(struct clk_functions * custom_clocks)

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