perf vendor events intel: Update BroadwellX events to V13 (97d00f2d) · Commits · 戴 / test

tools/perf/pmu-events/arch/x86/broadwellx/cache.json

+203 −180

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json

+51 −57

Original line number	Diff line number	Diff line
		@@ -6,7 +6,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
		"Errata": "BDM30",
		"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
		"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		@@ -17,7 +17,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
		"Errata": "BDM30",
		"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
		"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		@@ -25,7 +25,6 @@
		"EventCode": "0xC7",
		"UMask": "0x1",
		"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
		"SampleAfterValue": "2000003",
		@@ -35,17 +34,24 @@
		"EventCode": "0xC7",
		"UMask": "0x2",
		"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
		"SampleAfterValue": "2000003",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xC7",
		"UMask": "0x3",
		"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
		"SampleAfterValue": "2000003",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xC7",
		"UMask": "0x4",
		"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
		"SampleAfterValue": "2000003",
		@@ -55,7 +61,6 @@
		"EventCode": "0xC7",
		"UMask": "0x8",
		"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
		"SampleAfterValue": "2000003",
		@@ -65,19 +70,54 @@
		"EventCode": "0xC7",
		"UMask": "0x10",
		"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
		"SampleAfterValue": "2000003",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xC7",
		"UMask": "0x15",
		"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
		"SampleAfterValue": "2000006",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xc7",
		"UMask": "0x20",
		"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
		"SampleAfterValue": "2000003",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xC7",
		"UMask": "0x2a",
		"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
		"SampleAfterValue": "2000005",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xC7",
		"UMask": "0x3c",
		"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.PACKED",
		"SampleAfterValue": "2000004",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xCA",
		"UMask": "0x2",
		"BriefDescription": "Number of X87 assists due to output value.",
		"Counter": "0,1,2,3",
		"EventName": "FP_ASSIST.X87_OUTPUT",
		"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
		"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		@@ -87,7 +127,7 @@
		"BriefDescription": "Number of X87 assists due to input value.",
		"Counter": "0,1,2,3",
		"EventName": "FP_ASSIST.X87_INPUT",
		"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
		"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		@@ -97,7 +137,7 @@
		"BriefDescription": "Number of SIMD FP assists due to Output values",
		"Counter": "0,1,2,3",
		"EventName": "FP_ASSIST.SIMD_OUTPUT",
		"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
		"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		@@ -107,7 +147,7 @@
		"BriefDescription": "Number of SIMD FP assists due to input values",
		"Counter": "0,1,2,3",
		"EventName": "FP_ASSIST.SIMD_INPUT",
		"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
		"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		@@ -121,51 +161,5 @@
		"PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xc7",
		"UMask": "0x20",
		"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
		"SampleAfterValue": "2000003",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xC7",
		"UMask": "0x3",
		"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
		"SampleAfterValue": "2000003",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xC7",
		"UMask": "0x3c",
		"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.PACKED",
		"SampleAfterValue": "2000004",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xC7",
		"UMask": "0x2a",
		"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
		"SampleAfterValue": "2000005",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"EventCode": "0xC7",
		"UMask": "0x15",
		"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
		"Counter": "0,1,2,3",
		"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
		"SampleAfterValue": "2000006",
		"CounterHTOff": "0,1,2,3"
		}
		]
		No newline at end of file

tools/perf/pmu-events/arch/x86/broadwellx/frontend.json

+69 −69

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/broadwellx/memory.json

+35 −5

Original line number	Diff line number	Diff line
		@@ -95,7 +95,6 @@
		"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
		"Counter": "0,1,2,3",
		"EventName": "TX_EXEC.MISC1",
		"PublicDescription": "Unfriendly TSX abort triggered by a flowmarker.",
		"SampleAfterValue": "2000003",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		@@ -171,11 +170,11 @@
		{
		"EventCode": "0xc8",
		"UMask": "0x4",
		"BriefDescription": "Number of times HLE abort was triggered",
		"BriefDescription": "Number of times HLE abort was triggered (PEBS)",
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "HLE_RETIRED.ABORTED",
		"PublicDescription": "Number of times HLE abort was triggered.",
		"PublicDescription": "Number of times HLE abort was triggered (PEBS).",
		"SampleAfterValue": "2000003",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		@@ -252,11 +251,11 @@
		{
		"EventCode": "0xc9",
		"UMask": "0x4",
		"BriefDescription": "Number of times RTM abort was triggered",
		"BriefDescription": "Number of times RTM abort was triggered (PEBS)",
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "RTM_RETIRED.ABORTED",
		"PublicDescription": "Number of times RTM abort was triggered .",
		"PublicDescription": "Number of times RTM abort was triggered (PEBS).",
		"SampleAfterValue": "2000003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -439,6 +438,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all requests that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -451,6 +451,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -463,6 +464,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -475,6 +477,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -487,6 +490,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -499,6 +503,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -511,6 +516,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -523,6 +529,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all demand & prefetch code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -535,6 +542,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -547,6 +555,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -559,6 +568,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -571,6 +581,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -583,6 +594,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -595,6 +607,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -607,6 +620,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all demand & prefetch data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -619,6 +633,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -631,6 +646,7 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -643,6 +659,20 @@
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		{
		"Offcore": "1",
		"EventCode": "0xB7, 0xBB",
		"UMask": "0x1",
		"BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3",
		"MSRValue": "0x3fbfc00002",
		"Counter": "0,1,2,3",
		"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
		"MSRIndex": "0x1a6,0x1a7",
		"PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		}

tools/perf/pmu-events/arch/x86/broadwellx/other.json

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