Commit 976e78a5 authored Sep 12, 2017 by Eugeniy Paltsev Committed by Vineet Gupta Oct 03, 2017

ARC: [plat-axs10x] sdio: Temporary fix of sdio ciu frequency

DW sdio controller has external ciu clock divider controlled
via register in SDIO IP. It divides sdio_ref_clk
(which comes from CGU) by 16 for default. So default mmcclk
clock (which comes to sdk_in) is 25000000 Hz.

So fix wrong current value (50000000 Hz) to actual 25000000 Hz.

Note this is a preventive fix, in line with similar change for HSDK
where this was actually needed. see:
http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002924.html



Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

parent 6afa3bcf

arch/arc/boot/dts/axs10x_mb.dtsi

+8 −1

Original line number	Diff line number	Diff line
		@@ -44,7 +44,14 @@

		mmcclk: mmcclk {
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
		/*
		* DW sdio controller has external ciu clock divider
		* controlled via register in SDIO IP. It divides
		* sdio_ref_clk (which comes from CGU) by 16 for
		* default. So default mmcclk clock (which comes
		* to sdk_in) is 25000000 Hz.
		*/
		clock-frequency = <25000000>;
		#clock-cells = <0>;
		};

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