Commit 6afa3bcf authored Sep 08, 2017 by Eugeniy Paltsev Committed by Vineet Gupta Oct 03, 2017

ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency



DW sdio controller has external ciu clock divider controlled via
register in SDIO IP. Due to its unexpected default value
(it should divide by 1 but it divides by 8)
SDIO IP uses wrong ciu clock and works unstable

So add temporary fix and change clock frequency from 100000000
to 12500000 Hz until we fix dw sdio driver itself.

Fixes SNPS STAR 9001204800

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

parent 043d1e72

arch/arc/boot/dts/hsdk.dts

+11 −1

Original line number	Diff line number	Diff line
		@@ -120,7 +120,17 @@

		mmcclk_ciu: mmcclk-ciu {
		compatible = "fixed-clock";
		clock-frequency = <100000000>;
		/*
		* DW sdio controller has external ciu clock divider
		* controlled via register in SDIO IP. Due to its
		* unexpected default value (it should devide by 1
		* but it devides by 8) SDIO IP uses wrong clock and
		* works unstable (see STAR 9001204800)
		* So add temporary fix and change clock frequency
		* from 100000000 to 12500000 Hz until we fix dw sdio
		* driver itself.
		*/
		clock-frequency = <12500000>;
		#clock-cells = <0>;
		};

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