Commit 95135bfa authored by Hauke Mehrtens's avatar Hauke Mehrtens Committed by Ralf Baechle
Browse files

MIPS: Lantiq: Deactivate most of the devices by default 



When the SoC starts up most of the devices should be deactivated by the
PMU, they should be activated when they get used by their drivers. Some
devices should not get deactivate at startup like the serial, register
them in a special way.

Signed-off-by: default avatarHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: default avatarJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11386/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 61e371d8

arch/mips/lantiq/xway/sysctrl.c

+28 −21
Original line number Original line Diff line number Diff line
@@ -286,7 +286,7 @@ static int clkout_enable(struct clk *clk) 
}

}





/* manage the clock gates via PMU */

/* manage the clock gates via PMU */

static void clkdev_add_pmu(const char *dev, const char *con,

static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,

			   unsigned int module, unsigned int bits)

			   unsigned int module, unsigned int bits)

{

{

	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);

	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
@@ -298,6 +298,13 @@ static void clkdev_add_pmu(const char *dev, const char *con, 
	clk->disable = pmu_disable;

	clk->disable = pmu_disable;

	clk->module = module;

	clk->module = module;

	clk->bits = bits;

	clk->bits = bits;

	if (deactivate) {

		/*

		 * Disable it during the initialization. Module should enable

		 * when used

		 */

		pmu_disable(clk);

	}

	clkdev_add(&clk->cl);

	clkdev_add(&clk->cl);

}

}
@@ -416,13 +423,13 @@ void __init ltq_soc_init(void) 
	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);

	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);





	/* add our generic xway clocks */

	/* add our generic xway clocks */

	clkdev_add_pmu("10000000.fpi", NULL, 0, PMU_FPI);

	clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);

	clkdev_add_pmu("1e100400.serial", NULL, 0, PMU_ASC0);

	clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);

	clkdev_add_pmu("1e100a00.gptu", NULL, 0, PMU_GPT);

	clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);

	clkdev_add_pmu("1e100bb0.stp", NULL, 0, PMU_STP);

	clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);

	clkdev_add_pmu("1e104100.dma", NULL, 0, PMU_DMA);

	clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);

	clkdev_add_pmu("1e100800.spi", NULL, 0, PMU_SPI);

	clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);

	clkdev_add_pmu("1e105300.ebu", NULL, 0, PMU_EBU);

	clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);

	clkdev_add_clkout();

	clkdev_add_clkout();





	/* add the soc dependent clocks */

	/* add the soc dependent clocks */
@@ -430,11 +437,11 @@ void __init ltq_soc_init(void) 
		ifccr = CGU_IFCCR_VR9;

		ifccr = CGU_IFCCR_VR9;

		pcicr = CGU_PCICR_VR9;

		pcicr = CGU_PCICR_VR9;

	} else {

	} else {

		clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE);

		clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);

	}

	}





	if (!of_machine_is_compatible("lantiq,ase")) {

	if (!of_machine_is_compatible("lantiq,ase")) {

		clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1);

		clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);

		clkdev_add_pci();

		clkdev_add_pci();

	}

	}
@@ -446,25 +453,25 @@ void __init ltq_soc_init(void) 
			clkdev_add_static(CLOCK_133M, CLOCK_133M,

			clkdev_add_static(CLOCK_133M, CLOCK_133M,

						CLOCK_133M, CLOCK_133M);

						CLOCK_133M, CLOCK_133M);

		clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),

		clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),

		clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);

		clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);

	} else if (of_machine_is_compatible("lantiq,vr9")) {

	} else if (of_machine_is_compatible("lantiq,vr9")) {

		clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),

		clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),

				ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());

				ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());

		clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);

		clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);

		clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);

		clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);

		clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);

		clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);

		clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI);

		clkdev_add_pmu("1d900000.pcie", "pdi", 1, 1, PMU1_PCIE_PDI);

		clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL);

		clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);

		clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);

		clkdev_add_pmu("1d900000.pcie", "ahb", 1, 0, PMU_AHBM | PMU_AHBS);

		clkdev_add_pmu("1e108000.eth", NULL, 0,

		clkdev_add_pmu("1e108000.eth", NULL, 1, 0,

				PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |

				PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |

				PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |

				PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |

				PMU_PPE_QSB | PMU_PPE_TOP);

				PMU_PPE_QSB | PMU_PPE_TOP);

		clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);

		clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);

	} else if (of_machine_is_compatible("lantiq,ar9")) {

	} else if (of_machine_is_compatible("lantiq,ar9")) {

		clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),

		clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),

				ltq_ar9_fpi_hz(), CLOCK_250M);

				ltq_ar9_fpi_hz(), CLOCK_250M);

		clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);

		clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);

	} else {

	} else {

		clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),

		clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),

				ltq_danube_fpi_hz(), ltq_danube_pp32_hz());

				ltq_danube_fpi_hz(), ltq_danube_pp32_hz());

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