MIPS: Lantiq: Add clock detection for grx390 and ar10 (61e371d8) · Commits · 戴 / test

arch/mips/lantiq/clk.h

+11 −0

Original line number	Diff line number	Diff line
		@@ -34,12 +34,15 @@
		#define CLOCK_288M 288888888
		#define CLOCK_300M 300000000
		#define CLOCK_333M 333333333
		#define CLOCK_360M 360000000
		#define CLOCK_393M 393215332
		#define CLOCK_400M 400000000
		#define CLOCK_432M 432000000
		#define CLOCK_450M 450000000
		#define CLOCK_500M 500000000
		#define CLOCK_600M 600000000
		#define CLOCK_666M 666666666
		#define CLOCK_720M 720000000

		/* clock out speeds */
		#define CLOCK_32_768K 32768
		@@ -82,4 +85,12 @@ extern unsigned long ltq_vr9_cpu_hz(void);
		extern unsigned long ltq_vr9_fpi_hz(void);
		extern unsigned long ltq_vr9_pp32_hz(void);

		extern unsigned long ltq_ar10_cpu_hz(void);
		extern unsigned long ltq_ar10_fpi_hz(void);
		extern unsigned long ltq_ar10_pp32_hz(void);

		extern unsigned long ltq_grx390_cpu_hz(void);
		extern unsigned long ltq_grx390_fpi_hz(void);
		extern unsigned long ltq_grx390_pp32_hz(void);

		#endif

arch/mips/lantiq/xway/clk.c

+156 −1

Original line number	Diff line number	Diff line
		@@ -28,7 +28,7 @@ static unsigned int ram_clocks[] = {

		/* vr9, ar10/grx390 clock */
		#define CGU_SYS_XRX 0x0c
		#define CGU_IF_CLK_VR9 0x24
		#define CGU_IF_CLK_AR10 0x24

		unsigned long ltq_danube_fpi_hz(void)
		{
		@@ -195,3 +195,158 @@ unsigned long ltq_vr9_pp32_hz(void)

		return clk;
		}

		unsigned long ltq_ar10_cpu_hz(void)
		{
		unsigned int clksys;
		int cpu_fs = (ltq_cgu_r32(CGU_SYS_XRX) >> 8) & 0x1;
		int freq_div = (ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0x7;

		switch (cpu_fs) {
		case 0:
		clksys = CLOCK_500M;
		break;
		case 1:
		clksys = CLOCK_600M;
		break;
		default:
		clksys = CLOCK_500M;
		break;
		}

		switch (freq_div) {
		case 0:
		return clksys;
		case 1:
		return clksys >> 1;
		case 2:
		return clksys >> 2;
		default:
		return clksys;
		}
		}

		unsigned long ltq_ar10_fpi_hz(void)
		{
		int freq_fpi = (ltq_cgu_r32(CGU_IF_CLK_AR10) >> 25) & 0xf;

		switch (freq_fpi) {
		case 1:
		return CLOCK_300M;
		case 5:
		return CLOCK_250M;
		case 2:
		return CLOCK_150M;
		case 6:
		return CLOCK_125M;

		default:
		return CLOCK_125M;
		}
		}

		unsigned long ltq_ar10_pp32_hz(void)
		{
		unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
		unsigned long clk;

		switch (clksys) {
		case 1:
		clk = CLOCK_250M;
		break;
		case 4:
		clk = CLOCK_400M;
		break;
		default:
		clk = CLOCK_250M;
		break;
		}

		return clk;
		}

		unsigned long ltq_grx390_cpu_hz(void)
		{
		unsigned int clksys;
		int cpu_fs = ((ltq_cgu_r32(CGU_SYS_XRX) >> 9) & 0x3);
		int freq_div = ((ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0x7);

		switch (cpu_fs) {
		case 0:
		clksys = CLOCK_600M;
		break;
		case 1:
		clksys = CLOCK_666M;
		break;
		case 2:
		clksys = CLOCK_720M;
		break;
		default:
		clksys = CLOCK_600M;
		break;
		}

		switch (freq_div) {
		case 0:
		return clksys;
		case 1:
		return clksys >> 1;
		case 2:
		return clksys >> 2;
		default:
		return clksys;
		}
		}

		unsigned long ltq_grx390_fpi_hz(void)
		{
		/* fpi clock is derived from ddr_clk */
		unsigned int clksys;
		int cpu_fs = ((ltq_cgu_r32(CGU_SYS_XRX) >> 9) & 0x3);
		int freq_div = ((ltq_cgu_r32(CGU_SYS_XRX)) & 0x7);
		switch (cpu_fs) {
		case 0:
		clksys = CLOCK_600M;
		break;
		case 1:
		clksys = CLOCK_666M;
		break;
		case 2:
		clksys = CLOCK_720M;
		break;
		default:
		clksys = CLOCK_600M;
		break;
		}

		switch (freq_div) {
		case 1:
		return clksys >> 1;
		case 2:
		return clksys >> 2;
		default:
		return clksys >> 1;
		}
		}

		unsigned long ltq_grx390_pp32_hz(void)
		{
		unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
		unsigned long clk;

		switch (clksys) {
		case 1:
		clk = CLOCK_250M;
		break;
		case 2:
		clk = CLOCK_432M;
		break;
		case 4:
		clk = CLOCK_400M;
		break;
		default:
		clk = CLOCK_250M;
		break;
		}
		return clk;
		}

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