Commit 18a3af60 authored by Hauke Mehrtens's avatar Hauke Mehrtens Committed by Ralf Baechle
Browse files

MIPS: Lantiq: Fix pp32 clock on vr9 



The vendor code uses different clock values for this clock.

Signed-off-by: default avatarHauke Mehrtens <hauke.mehrtens@lantiq.com>
Acked-by: default avatarJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11384/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b5a03d0c

arch/mips/lantiq/clk.h

+2 −0
Original line number Diff line number Diff line
@@ -31,10 +31,12 @@ 
#define CLOCK_240M	240000000

#define CLOCK_250M	250000000

#define CLOCK_266M	266666666

#define CLOCK_288M	288888888

#define CLOCK_300M	300000000

#define CLOCK_333M	333333333

#define CLOCK_393M	393215332

#define CLOCK_400M	400000000

#define CLOCK_432M	432000000

#define CLOCK_450M	450000000

#define CLOCK_500M	500000000

#define CLOCK_600M	600000000

arch/mips/lantiq/xway/clk.c

+6 −3
Original line number Diff line number Diff line
@@ -175,15 +175,18 @@ unsigned long ltq_vr9_fpi_hz(void) 


unsigned long ltq_vr9_pp32_hz(void)

{

	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3;

	unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;

	unsigned long clk;



	switch (clksys) {

	case 0:

		clk = CLOCK_500M;

		break;

	case 1:

		clk = CLOCK_450M;

		clk = CLOCK_432M;

		break;

	case 2:

		clk = CLOCK_300M;

		clk = CLOCK_288M;

		break;

	default:

		clk = CLOCK_500M;

CRA Git | Maintained and supported by SUSTech CRA and CCSE