Commit 94dd54c5 authored Dec 21, 2019 by Christophe Leroy Committed by Michael Ellerman Jan 27, 2020

powerpc/32s: Avoid crossing page boundary while changing SRR0/1.



Trying VMAP_STACK with KVM, vmlinux was not starting.
This was due to SRR0 and SRR1 clobbered by an ISI due to
the rfi being in a different page than the mtsrr0/1:

c0003fe0 <mmu_off>:
c0003fe0:       38 83 00 54     addi    r4,r3,84
c0003fe4:       7c 60 00 a6     mfmsr   r3
c0003fe8:       70 60 00 30     andi.   r0,r3,48
c0003fec:       4d 82 00 20     beqlr
c0003ff0:       7c 63 00 78     andc    r3,r3,r0
c0003ff4:       7c 9a 03 a6     mtsrr0  r4
c0003ff8:       7c 7b 03 a6     mtsrr1  r3
c0003ffc:       7c 00 04 ac     hwsync
c0004000:       4c 00 00 64     rfi

Align the 4 instruction block used to deactivate MMU to order 4,
so that the block never crosses a page boundary.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/30d2cda111b7977227fff067fa7e358440e2b3a4.1576916812.git.christophe.leroy@c-s.fr

parent 2e15001e

arch/powerpc/kernel/head_32.S

+6 −0

Original line number	Diff line number	Diff line
		@@ -917,6 +917,8 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
		ori r4,r4,2f@l
		tophys(r4,r4)
		li r3,MSR_KERNEL & ~(MSR_IR\|MSR_DR)

		.align 4
		mtspr SPRN_SRR0,r4
		mtspr SPRN_SRR1,r3
		SYNC
		@@ -1058,6 +1060,8 @@ _ENTRY(update_bats)
		rlwinm r0, r6, 0, ~MSR_RI
		rlwinm r0, r0, 0, ~MSR_EE
		mtmsr r0

		.align 4
		mtspr SPRN_SRR0, r4
		mtspr SPRN_SRR1, r3
		SYNC
		@@ -1097,6 +1101,8 @@ mmu_off:
		andi. r0,r3,MSR_DR\|MSR_IR /* MMU enabled? */
		beqlr
		andc r3,r3,r0

		.align 4
		mtspr SPRN_SRR0,r4
		mtspr SPRN_SRR1,r3
		sync

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