clk: meson: meson8b: add the video clock tables - WiP

WiP:
- HDMI PLL M/N tables and init regs
- divider tables

Add all known clock tables from Amlogic's 3.10 vendor kernel:
- reg_sequence to initialize the HDMI PLL with the settings for a video
  mode that doesn't require PLL internal clock doubling (taken from
  the vendor driver's 1080P mode)
- pll_params_table contains all M/N combinations found in the endlessm
  kernel (which seems to contain additional settings for some VESA and
  75Hz display modes)
- vid_pll_pre_div can divide by 5 or 6 and if u-boot did not initialize
  this clock then it divides by 1 by default (only 5 and 6 are used at
  runtime by the vendor kernel)
- vid_pll_post_div can divide by either 1 or 2 (only these two values
  are used in the vendor kernel)
- vid_pll_final_div can divide by 1, 2 and 4 (only these three values
  are used in the vendor kernel)

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>