Commit 909a6065 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-next-5.5-2019-12-03' of git://people.freedesktop.org/~agd5f/linux into drm-next 



drm-next-5.5-2019-12-03:

amdgpu:
- Fix vram lost handling with BACO on VI/CI asics
- DC fixes for Navi14
- Misc gfx10 fixes
- SR-IOV fixes
- Fix driver unload
- Fix XGMI limits on Arcturus

amdkfd:
- Enable KFD on PPC
- Optimize KFD page table reservations

radeon:
- Fix register checker for r1xx/r2xx

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191203204135.5437-1-alexander.deucher@amd.com
parents 3e25dbca 008037d4

MAINTAINERS

+0 −1
Original line number Diff line number Diff line
@@ -856,7 +856,6 @@ S: Maintained 
F:	drivers/i2c/busses/i2c-amd-mp2*















AMD POWERPLAY













M:	Rex Zhu <rex.zhu@amd.com>















M:	Evan Quan <evan.quan@amd.com>















L:	amd-gfx@lists.freedesktop.org















S:	Supported

































drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c



+14
−1






























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@@ -105,11 +105,24 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void)













		(kfd_mem_limit.max_ttm_mem_limit >> 20));















}





























/* Estimate page table size needed to represent a given memory size













 *













 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory













 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB













 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize













 * for 2MB pages for TLB efficiency. However, small allocations and













 * fragmented system memory still need some 4KB pages. We choose a













 * compromise that should work in most cases without reserving too













 * much memory for page tables unnecessarily (factor 16K, >> 14).













 */













#define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14)





























static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,















		uint64_t size, u32 domain, bool sg)















{













	uint64_t reserved_for_pt =













		ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);















	size_t acc_size, system_mem_needed, ttm_mem_needed, vram_needed;













	uint64_t reserved_for_pt = amdgpu_amdkfd_total_mem_size >> 9;















	int ret = 0;































	acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,

































drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c



+2
−2






























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@@ -1487,8 +1487,8 @@ out:













			return ret;































		/* Start rlc autoload after psp recieved all the gfx firmware */













		if (psp->autoload_supported && ucode->ucode_id ==













			AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {













		if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?













		    AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {















			ret = psp_rlc_autoload(psp);















			if (ret) {















				DRM_ERROR("Failed to start rlc autoload\n");

































drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c



+12
−5






























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@@ -27,7 +27,8 @@













#include <linux/bits.h>















#include "smu_v11_0_i2c.h"





























#define EEPROM_I2C_TARGET_ADDR 0xA0













#define EEPROM_I2C_TARGET_ADDR_ARCTURUS  0xA8













#define EEPROM_I2C_TARGET_ADDR_VEGA20    0xA0































/*















 * The 2 macros bellow represent the actual size in bytes that










@@ -83,7 +84,7 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,













{















	int ret = 0;















	struct i2c_msg msg = {













			.addr	= EEPROM_I2C_TARGET_ADDR,













			.addr	= 0,















			.flags	= 0,















			.len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,















			.buf	= buff,









@@ -93,6 +94,8 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,













	*(uint16_t *)buff = EEPROM_HDR_START;















	__encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);





























	msg.addr = control->i2c_address;





























	ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);















	if (ret < 1)















		DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret);










@@ -203,7 +206,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)













	unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };















	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;















	struct i2c_msg msg = {













			.addr	= EEPROM_I2C_TARGET_ADDR,













			.addr	= 0,















			.flags	= I2C_M_RD,















			.len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,















			.buf	= buff,









@@ -213,10 +216,12 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)





























	switch (adev->asic_type) {















	case CHIP_VEGA20:













		control->i2c_address = EEPROM_I2C_TARGET_ADDR_VEGA20;















		ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);















		break;































	case CHIP_ARCTURUS:













		control->i2c_address = EEPROM_I2C_TARGET_ADDR_ARCTURUS;















		ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor);















		break;

























@@ -229,6 +234,8 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)













		return ret;















	}





























	msg.addr = control->i2c_address;





























	/* Read/Create table header from EEPROM address 0 */















	ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);















	if (ret < 1) {










@@ -408,7 +415,7 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,













		 * Update bits 16,17 of EEPROM address in I2C address by setting them















		 * to bits 1,2 of Device address byte















		 */













		msg->addr = EEPROM_I2C_TARGET_ADDR |













		msg->addr = control->i2c_address |















			        ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);















		msg->flags	= write ? 0 : I2C_M_RD;















		msg->len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE;

































drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h



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@@ -50,6 +50,7 @@ struct amdgpu_ras_eeprom_control {













	struct mutex tbl_mutex;















	bool bus_locked;















	uint32_t tbl_byte_sum;













	uint16_t i2c_address; // 8-bit represented address















};































/*









































































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