Commit 3e25dbca authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2019-11-28' of...

Merge tag 'drm-intel-next-fixes-2019-11-28' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

- Important fix to uAPI alignment on query IOCTL
- Fixes for the power regression introduced by the previous security patches
- Avoid regressing super heavy benchmarks by increasing the default request pre-emption timeout from 100 ms to 640 ms to
- Resulting set of smaller fixes done while problem was inspected
- Display fixes for EHL voltage level programming and TGL DKL PHY vswing for HDMI

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191128141524.GA11992@jlahtine-desk.ger.corp.intel.com
parents 36a170b1 3cc44feb
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+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ config DRM_I915_HEARTBEAT_INTERVAL

config DRM_I915_PREEMPT_TIMEOUT
	int "Preempt timeout (ms, jiffy granularity)"
	default 100 # milliseconds
	default 640 # milliseconds
	help
	  How long to wait (in milliseconds) for a preemption event to occur
	  when submitting a new context via execlists. If the current context
+3 −1
Original line number Diff line number Diff line
@@ -1273,7 +1273,9 @@ static u8 icl_calc_voltage_level(int cdclk)

static u8 ehl_calc_voltage_level(int cdclk)
{
	if (cdclk > 312000)
	if (cdclk > 326400)
		return 3;
	else if (cdclk > 312000)
		return 2;
	else if (cdclk > 180000)
		return 1;
+24 −5
Original line number Diff line number Diff line
@@ -593,7 +593,7 @@ struct tgl_dkl_phy_ddi_buf_trans {
	u32 dkl_de_emphasis_control;
};

static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_ddi_translations[] = {
static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
				/* VS	pre-emp	Non-trans mV	Pre-emph dB */
	{ 0x7, 0x0, 0x00 },	/* 0	0	400mV		0 dB */
	{ 0x5, 0x0, 0x03 },	/* 0	1	400mV		3.5 dB */
@@ -607,6 +607,20 @@ static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_ddi_translations[] = {
	{ 0x0, 0x0, 0x00 },	/* 3	0	1200mV		0 dB HDMI default */
};

static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
				/* HDMI Preset	VS	Pre-emph */
	{ 0x7, 0x0, 0x0 },	/* 1		400mV	0dB */
	{ 0x6, 0x0, 0x0 },	/* 2		500mV	0dB */
	{ 0x4, 0x0, 0x0 },	/* 3		650mV	0dB */
	{ 0x2, 0x0, 0x0 },	/* 4		800mV	0dB */
	{ 0x0, 0x0, 0x0 },	/* 5		1000mV	0dB */
	{ 0x0, 0x0, 0x5 },	/* 6		Full	-1.5 dB */
	{ 0x0, 0x0, 0x6 },	/* 7		Full	-1.8 dB */
	{ 0x0, 0x0, 0x7 },	/* 8		Full	-2 dB */
	{ 0x0, 0x0, 0x8 },	/* 9		Full	-2.5 dB */
	{ 0x0, 0x0, 0xA },	/* 10		Full	-3 dB */
};

static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
{
@@ -898,7 +912,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
						0, &n_entries);
		else
			n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
			n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
		default_entry = n_entries - 1;
	} else if (INTEL_GEN(dev_priv) == 11) {
		if (intel_phy_is_combo(dev_priv, phy))
@@ -2371,7 +2385,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
			icl_get_combo_buf_trans(dev_priv, encoder->type,
						intel_dp->link_rate, &n_entries);
		else
			n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
			n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
	} else if (INTEL_GEN(dev_priv) == 11) {
		if (intel_phy_is_combo(dev_priv, phy))
			icl_get_combo_buf_trans(dev_priv, encoder->type,
@@ -2823,8 +2837,13 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
	u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;

	n_entries = ARRAY_SIZE(tgl_dkl_phy_ddi_translations);
	ddi_translations = tgl_dkl_phy_ddi_translations;
	if (encoder->type == INTEL_OUTPUT_HDMI) {
		n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
		ddi_translations = tgl_dkl_phy_hdmi_ddi_trans;
	} else {
		n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
		ddi_translations = tgl_dkl_phy_dp_ddi_trans;
	}

	if (level >= n_entries)
		level = n_entries - 1;
+17 −4
Original line number Diff line number Diff line
@@ -310,10 +310,23 @@ int intel_context_prepare_remote_request(struct intel_context *ce,
	GEM_BUG_ON(rq->hw_context == ce);

	if (rcu_access_pointer(rq->timeline) != tl) { /* timeline sharing! */
		err = mutex_lock_interruptible_nested(&tl->mutex,
						      SINGLE_DEPTH_NESTING);
		if (err)
			return err;
		/*
		 * Ideally, we just want to insert our foreign fence as
		 * a barrier into the remove context, such that this operation
		 * occurs after all current operations in that context, and
		 * all future operations must occur after this.
		 *
		 * Currently, the timeline->last_request tracking is guarded
		 * by its mutex and so we must obtain that to atomically
		 * insert our barrier. However, since we already hold our
		 * timeline->mutex, we must be careful against potential
		 * inversion if we are the kernel_context as the remote context
		 * will itself poke at the kernel_context when it needs to
		 * unpin. Ergo, if already locked, we drop both locks and
		 * try again (through the magic of userspace repeating EAGAIN).
		 */
		if (!mutex_trylock(&tl->mutex))
			return -EAGAIN;

		/* Queue this switch after current activity by this context. */
		err = i915_active_fence_set(&tl->last_request, rq);
+1 −3
Original line number Diff line number Diff line
@@ -100,9 +100,7 @@ execlists_num_ports(const struct intel_engine_execlists * const execlists)
static inline struct i915_request *
execlists_active(const struct intel_engine_execlists *execlists)
{
	GEM_BUG_ON(execlists->active - execlists->inflight >
		   execlists_num_ports(execlists));
	return READ_ONCE(*execlists->active);
	return *READ_ONCE(execlists->active);
}

static inline void
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