Commit 36a170b1 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2019-11-05' of https://gitlab.freedesktop.org/drm/msm into drm-next 



+ OCMEM support to enable the couple generations that had shared OCMEM
  rather than GMEM exclusively for the GPU (late a3xx and I think basically
  all of a4xx).  Bjorn and Brian decided to land this through the drm
  tree to avoid having to coordinate merge requests.
+ a510 support, and various associated display support
+ the usual misc cleanups and fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ <CAF6AEGv-JWswEJRxe5AmnGQO1SZnpxK05kO1E29K6UUzC9GMMw@mail.gmail.com
parents acc61b89 e20c9284

Documentation/devicetree/bindings/display/msm/gmu.txt

+51 −0
Original line number Diff line number Diff line
@@ -31,6 +31,10 @@ Required properties: 
- iommus: phandle to the adreno iommu

- operating-points-v2: phandle to the OPP operating points



Optional properties:

- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon

        SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.



Example:



/ {
@@ -63,3 +67,50 @@ Example: 
		operating-points-v2 = <&gmu_opp_table>;

	};

};



a3xx example with OCMEM support:



/ {

	...



	gpu: adreno@fdb00000 {

		compatible = "qcom,adreno-330.2",

		             "qcom,adreno";

		reg = <0xfdb00000 0x10000>;

		reg-names = "kgsl_3d0_reg_memory";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "kgsl_3d0_irq";

		clock-names = "core",

		              "iface",

		              "mem_iface";

		clocks = <&mmcc OXILI_GFX3D_CLK>,

		         <&mmcc OXILICX_AHB_CLK>,

		         <&mmcc OXILICX_AXI_CLK>;

		sram = <&gmu_sram>;

		power-domains = <&mmcc OXILICX_GDSC>;

		operating-points-v2 = <&gpu_opp_table>;

		iommus = <&gpu_iommu 0>;

	};



	ocmem@fdd00000 {

		compatible = "qcom,msm8974-ocmem";



		reg = <0xfdd00000 0x2000>,

		      <0xfec00000 0x180000>;

		reg-names = "ctrl",

		             "mem";



		clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,

		         <&mmcc OCMEMCX_OCMEMNOC_CLK>;

		clock-names = "core",

		              "iface";



		#address-cells = <1>;

		#size-cells = <1>;



		gmu_sram: gmu-sram@0 {

			reg = <0x0 0x100000>;

			ranges = <0 0 0xfec00000 0x100000>;

		};

	};

};

Documentation/devicetree/bindings/display/msm/mdp5.txt

+2 −0
Original line number Diff line number Diff line
@@ -76,6 +76,8 @@ Required properties: 
Optional properties:

- clock-names: the following clocks are optional:

  * "lut"

  * "tbu"

  * "tbu_rt"



Example:

Documentation/devicetree/bindings/sram/qcom,ocmem.yaml

0 → 100644
+96 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/sram/qcom,ocmem.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: On Chip Memory (OCMEM) that is present on some Qualcomm Snapdragon SoCs.



maintainers:

  - Brian Masney <masneyb@onstation.org>



description: |

  The On Chip Memory (OCMEM) is typically used by the GPU, camera/video, and

  audio components on some Snapdragon SoCs.



properties:

  compatible:

    const: qcom,msm8974-ocmem



  reg:

    items:

      - description: Control registers

      - description: OCMEM address range



  reg-names:

    items:

      - const: ctrl

      - const: mem



  clocks:

    items:

      - description: Core clock

      - description: Interface clock



  clock-names:

    items:

      - const: core

      - const: iface



  '#address-cells':

    const: 1



  '#size-cells':

    const: 1



required:

  - compatible

  - reg

  - reg-names

  - clocks

  - clock-names

  - '#address-cells'

  - '#size-cells'



patternProperties:

  "^.+-sram$":

    type: object

    description: A region of reserved memory.



    properties:

      reg:

        maxItems: 1



      ranges:

        maxItems: 1



    required:

      - reg

      - ranges



examples:

  - |

      #include <dt-bindings/clock/qcom,rpmcc.h>

      #include <dt-bindings/clock/qcom,mmcc-msm8974.h>



      ocmem: ocmem@fdd00000 {

        compatible = "qcom,msm8974-ocmem";



        reg = <0xfdd00000 0x2000>,

              <0xfec00000 0x180000>;

        reg-names = "ctrl",

                    "mem";



        clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,

                 <&mmcc OCMEMCX_OCMEMNOC_CLK>;

        clock-names = "core",

                      "iface";



        #address-cells = <1>;

        #size-cells = <1>;



        gmu-sram@0 {

                reg = <0x0 0x100000>;

                ranges = <0 0 0xfec00000 0x100000>;

        };

      };

drivers/firmware/qcom_scm-32.c

+51 −1
Original line number Diff line number Diff line
@@ -442,6 +442,41 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, 
		req, req_cnt * sizeof(*req), resp, sizeof(*resp));

}



int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset, u32 size,

			  u32 mode)

{

	struct ocmem_tz_lock {

		__le32 id;

		__le32 offset;

		__le32 size;

		__le32 mode;

	} request;



	request.id = cpu_to_le32(id);

	request.offset = cpu_to_le32(offset);

	request.size = cpu_to_le32(size);

	request.mode = cpu_to_le32(mode);



	return qcom_scm_call(dev, QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_LOCK_CMD,

			     &request, sizeof(request), NULL, 0);

}



int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset, u32 size)

{

	struct ocmem_tz_unlock {

		__le32 id;

		__le32 offset;

		__le32 size;

	} request;



	request.id = cpu_to_le32(id);

	request.offset = cpu_to_le32(offset);

	request.size = cpu_to_le32(size);



	return qcom_scm_call(dev, QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_UNLOCK_CMD,

			     &request, sizeof(request), NULL, 0);

}



void __qcom_scm_init(void)

{

}
@@ -582,7 +617,22 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, 
int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,

			       u32 spare)

{

	return -ENODEV;

	struct msm_scm_sec_cfg {

		__le32 id;

		__le32 ctx_bank_num;

	} cfg;

	int ret, scm_ret = 0;



	cfg.id = cpu_to_le32(device_id);

	cfg.ctx_bank_num = cpu_to_le32(spare);



	ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_RESTORE_SEC_CFG,

			    &cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret));



	if (ret || scm_ret)

		return ret ? ret : -EINVAL;



	return 0;

}



int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,

drivers/firmware/qcom_scm-64.c

+12 −0
Original line number Diff line number Diff line
@@ -241,6 +241,18 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, 
	return ret;

}



int __qcom_scm_ocmem_lock(struct device *dev, uint32_t id, uint32_t offset,

			  uint32_t size, uint32_t mode)

{

	return -ENOTSUPP;

}



int __qcom_scm_ocmem_unlock(struct device *dev, uint32_t id, uint32_t offset,

			    uint32_t size)

{

	return -ENOTSUPP;

}



void __qcom_scm_init(void)

{

	u64 cmd;

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