Commit 907ba6a1 authored by Yong Wu's avatar Yong Wu Committed by Joerg Roedel
Browse files

iommu/mediatek: Add mt8183 IOMMU support 



The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use
the ARM Short-descriptor like mt8173, and most of the HW registers
are the same.

Here list main differences between mt8183 and mt8173/mt2712:
1) mt8183 has only one M4U HW like mt8173 while mt2712 has two.
2) mt8183 don't have the "bclk" clock, it use the EMI clock instead.
3) mt8183 can support the dram over 4GB, but it doesn't call this "4GB
mode".
4) mt8183 pgtable base register(0x0) extend bit[1:0] which represent
the bit[33:32] in the physical address of the pgtable base, But the
standard ttbr0[1] means the S bit which is enabled defaultly, Hence,
we add a mask.
5) mt8183 HW has a GALS modules, SMI should enable "has_gals" support.
6) mt8183 need reset_axi like mt8173.
7) the larb-id in smi-common is remapped. M4U should add its larbid_remap.

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarEvan Green <evgreen@chromium.org>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 64fea74a

drivers/iommu/mtk_iommu.c

+12 −3
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include "mtk_iommu.h"



#define REG_MMU_PT_BASE_ADDR			0x000

#define MMU_PT_ADDR_MASK			GENMASK(31, 7)



#define REG_MMU_INVALIDATE			0x020

#define F_ALL_INVLD				0x2
@@ -357,7 +358,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, 
	/* Update the pgtable base address register of the M4U HW */

	if (!data->m4u_dom) {

		data->m4u_dom = dom;

		writel(dom->cfg.arm_v7s_cfg.ttbr[0],

		writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,

		       data->base + REG_MMU_PT_BASE_ADDR);

	}
@@ -737,6 +738,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) 
{

	struct mtk_iommu_data *data = dev_get_drvdata(dev);

	struct mtk_iommu_suspend_reg *reg = &data->reg;

	struct mtk_iommu_domain *m4u_dom = data->m4u_dom;

	void __iomem *base = data->base;

	int ret;
@@ -752,8 +754,8 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev) 
	writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);

	writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);

	writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);

	if (data->m4u_dom)

		writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],

	if (m4u_dom)

		writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK,

		       base + REG_MMU_PT_BASE_ADDR);

	return 0;

}
@@ -778,9 +780,16 @@ static const struct mtk_iommu_plat_data mt8173_data = { 
	.larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */

};



static const struct mtk_iommu_plat_data mt8183_data = {

	.m4u_plat     = M4U_MT8183,

	.reset_axi    = true,

	.larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1},

};



static const struct of_device_id mtk_iommu_of_ids[] = {

	{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},

	{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},

	{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},

	{}

};

drivers/iommu/mtk_iommu.h

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ enum mtk_iommu_plat { 
	M4U_MT2701,

	M4U_MT2712,

	M4U_MT8173,

	M4U_MT8183,

};



struct mtk_iommu_plat_data {

drivers/memory/mtk-smi.c

+20 −0
Original line number Diff line number Diff line
@@ -277,6 +277,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 
	.larb_direct_to_common_mask = BIT(8) | BIT(9),      /* bdpsys */

};



static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {

	.has_gals                   = true,

	.config_port                = mtk_smi_larb_config_port_gen2_general,

	.larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),

				      /* IPU0 | IPU1 | CCU */

};



static const struct of_device_id mtk_smi_larb_of_ids[] = {

	{

		.compatible = "mediatek,mt8173-smi-larb",
@@ -290,6 +297,10 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { 
		.compatible = "mediatek,mt2712-smi-larb",

		.data = &mtk_smi_larb_mt2712

	},

	{

		.compatible = "mediatek,mt8183-smi-larb",

		.data = &mtk_smi_larb_mt8183

	},

	{}

};
@@ -383,6 +394,11 @@ static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 
	.gen = MTK_SMI_GEN2,

};



static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {

	.gen      = MTK_SMI_GEN2,

	.has_gals = true,

};



static const struct of_device_id mtk_smi_common_of_ids[] = {

	{

		.compatible = "mediatek,mt8173-smi-common",
@@ -396,6 +412,10 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { 
		.compatible = "mediatek,mt2712-smi-common",

		.data = &mtk_smi_common_gen2,

	},

	{

		.compatible = "mediatek,mt8183-smi-common",

		.data = &mtk_smi_common_mt8183,

	},

	{}

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE