arm64: dts: amlogic: meson-gxm: add the Mali OPP table and use DVFS (8f16cfab) · Commits · 戴 / test

arch/arm64/boot/dts/amlogic/meson-gxm.dtsi

+30 −15

Original line number	Diff line number	Diff line
		@@ -82,6 +82,35 @@
		#cooling-cells = <2>;
		};
		};

		gpu_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-125000000 {
		opp-hz = /bits/ 64 <125000000>;
		opp-microvolt = <950000>;
		};
		opp-250000000 {
		opp-hz = /bits/ 64 <250000000>;
		opp-microvolt = <950000>;
		};
		opp-285714285 {
		opp-hz = /bits/ 64 <285714285>;
		opp-microvolt = <950000>;
		};
		opp-400000000 {
		opp-hz = /bits/ 64 <400000000>;
		opp-microvolt = <950000>;
		};
		opp-500000000 {
		opp-hz = /bits/ 64 <500000000>;
		opp-microvolt = <950000>;
		};
		opp-666666666 {
		opp-hz = /bits/ 64 <666666666>;
		opp-microvolt = <950000>;
		};
		};
		};

		&apb {
		@@ -106,21 +135,7 @@
		interrupt-names = "job", "mmu", "gpu";
		clocks = <&clkc CLKID_MALI>;
		resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;

		/*
		* Mali clocking is provided by two identical clock paths
		* MALI_0 and MALI_1 muxed to a single clock by a glitch
		* free mux to safely change frequency while running.
		*/
		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
		<&clkc CLKID_MALI_0>,
		<&clkc CLKID_MALI>; /* Glitch free mux */
		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
		<0>, /* Do Nothing */
		<&clkc CLKID_MALI_0>;
		assigned-clock-rates = <0>, /* Do Nothing */
		<666666666>,
		<0>; /* Do Nothing */
		operating-points-v2 = <&gpu_opp_table>;
		};
		};