Commit 46ffadc7 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman
Browse files

arm64: dts: amlogic: meson-gx: add the Mali-450 OPP table and use DVFS 



Add the OPP table for the Mali-450 GPU and drop the hardcoded initial
clock configuration. This enables GPU DVFS and thus saves power when the
GPU is not in use while still being able switch to a higher clock on
demand.

Set the GP0_PLL clock to 744MHz (which is the only frequency which
cannot be derived from the FCLK dividers) as the clock driver avoids
setting the parent clock rates so the MPLL clocks aren't changed (as
these are reserved for audio). The only exception to this is the GXL
S805X package because the 744MHz OPP isn't working correctly there.

While here, make most of meson-gxl-mali re-usable to reduce the amount
of duplicate code between GXBB and GXL. This is more important now as we
don't want to duplicate the GPU OPP table.

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200719173213.639540-2-martin.blumenstingl@googlemail.com
parent f26d8e7a

arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi

0 → 100644
+61 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright (c) 2017 BayLibre SAS

 * Author: Neil Armstrong <narmstrong@baylibre.com>

 */



/ {

	gpu_opp_table: opp-table {

		compatible = "operating-points-v2";



		opp-125000000 {

			opp-hz = /bits/ 64 <125000000>;

			opp-microvolt = <950000>;

		};

		opp-250000000 {

			opp-hz = /bits/ 64 <250000000>;

			opp-microvolt = <950000>;

		};

		opp-285714285 {

			opp-hz = /bits/ 64 <285714285>;

			opp-microvolt = <950000>;

		};

		opp-400000000 {

			opp-hz = /bits/ 64 <400000000>;

			opp-microvolt = <950000>;

		};

		opp-500000000 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <950000>;

		};

		opp-666666666 {

			opp-hz = /bits/ 64 <666666666>;

			opp-microvolt = <950000>;

		};

		opp-744000000 {

			opp-hz = /bits/ 64 <744000000>;

			opp-microvolt = <950000>;

		};

	};

};



&apb {

	mali: gpu@c0000 {

		compatible = "arm,mali-450";

		reg = <0x0 0xc0000 0x0 0x40000>;

		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "gp", "gpmmu", "pp", "pmu",

			"pp0", "ppmmu0", "pp1", "ppmmu1",

			"pp2", "ppmmu2";

		operating-points-v2 = <&gpu_opp_table>;

	};

};

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi

+11 −40
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 */



#include "meson-gx.dtsi"

#include "meson-gx-mali450.dtsi"

#include <dt-bindings/gpio/meson-gxbb-gpio.h>

#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>

#include <dt-bindings/clock/gxbb-clkc.h>
@@ -264,46 +265,6 @@ 
	};

};



&apb {

	mali: gpu@c0000 {

		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";

		reg = <0x0 0xc0000 0x0 0x40000>;

		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "gp", "gpmmu", "pp", "pmu",

			"pp0", "ppmmu0", "pp1", "ppmmu1",

			"pp2", "ppmmu2";

		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;

		clock-names = "bus", "core";



		/*

		 * Mali clocking is provided by two identical clock paths

		 * MALI_0 and MALI_1 muxed to a single clock by a glitch

		 * free mux to safely change frequency while running.

		 */

		assigned-clocks = <&clkc CLKID_GP0_PLL>,

				  <&clkc CLKID_MALI_0_SEL>,

				  <&clkc CLKID_MALI_0>,

				  <&clkc CLKID_MALI>; /* Glitch free mux */

		assigned-clock-parents = <0>, /* Do Nothing */

					 <&clkc CLKID_GP0_PLL>,

					 <0>, /* Do Nothing */

					 <&clkc CLKID_MALI_0>;

		assigned-clock-rates = <744000000>,

				       <0>, /* Do Nothing */

				       <744000000>,

				       <0>; /* Do Nothing */

	};

};



&cbus {

	spifc: spi@8c80 {

		compatible = "amlogic,meson-gxbb-spifc";
@@ -386,6 +347,16 @@ 
	clocks = <&clkc CLKID_I2C>;

};



&mali {

	compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";



	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;

	clock-names = "bus", "core";



	assigned-clocks = <&clkc CLKID_GP0_PLL>;

	assigned-clock-rates = <744000000>;

};



&periphs {

	pinctrl_periphs: pinctrl@4b0 {

		compatible = "amlogic,meson-gxbb-periphs-pinctrl";

arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi

+9 −37
Original line number Diff line number Diff line
@@ -4,42 +4,14 @@ 
 * Author: Neil Armstrong <narmstrong@baylibre.com>

 */



&apb {

	mali: gpu@c0000 {

#include "meson-gx-mali450.dtsi"



&mali {

	compatible = "amlogic,meson-gxl-mali", "arm,mali-450";

		reg = <0x0 0xc0000 0x0 0x40000>;

		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "gp", "gpmmu", "pp", "pmu",

			"pp0", "ppmmu0", "pp1", "ppmmu1",

			"pp2", "ppmmu2";



	clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;

	clock-names = "bus", "core";



		/*

		 * Mali clocking is provided by two identical clock paths

		 * MALI_0 and MALI_1 muxed to a single clock by a glitch

		 * free mux to safely change frequency while running.

		 */

		assigned-clocks = <&clkc CLKID_GP0_PLL>,

				  <&clkc CLKID_MALI_0_SEL>,

				  <&clkc CLKID_MALI_0>,

				  <&clkc CLKID_MALI>; /* Glitch free mux */

		assigned-clock-parents = <0>, /* Do Nothing */

					 <&clkc CLKID_GP0_PLL>,

					 <0>, /* Do Nothing */

					 <&clkc CLKID_MALI_0>;

		assigned-clock-rates = <744000000>,

				       <0>, /* Do Nothing */

				       <744000000>,

				       <0>; /* Do Nothing */

	};

	assigned-clocks = <&clkc CLKID_GP0_PLL>;

	assigned-clock-rates = <744000000>;

};

arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi

+8 −9
Original line number Diff line number Diff line
@@ -11,14 +11,13 @@ 
};



/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */

&gpu_opp_table {

	opp-744000000 {

		status = "disabled";

	};

};



&mali {

	assigned-clocks = <&clkc CLKID_MALI_0_SEL>,

			  <&clkc CLKID_MALI_0>,

			  <&clkc CLKID_MALI>; /* Glitch free mux */

	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,

				 <0>, /* Do Nothing */

				 <&clkc CLKID_MALI_0>;

	assigned-clock-rates = <0>, /* Do Nothing */

			       <666666666>,

			       <0>; /* Do Nothing */

	/delete-property/ assigned-clocks;

	/delete-property/ assigned-clock-rates;

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE