Merge branch 'arm-next' of git://git.xilinx.com/linux-xlnx into next/dt

Device Tree Clock bindings for the Zynq 7000 EPP

The Zynq EPP has several different clk providers, each with there own bindings.

The purpose of this document is to document their usage.

See clock_bindings.txt for more information on the generic clock bindings.

See Chapter 25 of Zynq TRM for more information about Zynq clocks.

== PLLs ==

Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.

Required properties:

- #clock-cells : shall be 0 (only one clock is output from this node)

- compatible : "xlnx,zynq-pll"

- reg : pair of u32 values, which are the address offsets within the SLCR

        of the relevant PLL_CTRL register and PLL_CFG register respectively

- clocks : phandle for parent clock.  should be the phandle for ps_clk

Optional properties:

- clock-output-names : name of the output clock

Example:

	armpll: armpll {

		#clock-cells = <0>;

		compatible = "xlnx,zynq-pll";

		clocks = <&ps_clk>;

		reg = <0x100 0x110>;

		clock-output-names = "armpll";

	};

== Peripheral clocks ==

Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.

Required properties:

- #clock-cells : shall be 1

- compatible : "xlnx,zynq-periph-clock"

- reg : a single u32 value, describing the offset within the SLCR where

        the CLK_CTRL register is found for this peripheral

- clocks : phandle for parent clocks.  should hold phandles for

           the IO_PLL, ARM_PLL, and DDR_PLL in order

- clock-output-names : names of the output clock(s).  For peripherals that have

                       two output clocks (for example, the UART), two clocks

                       should be listed.

Example:

	uart_clk: uart_clk {

		#clock-cells = <1>;

		compatible = "xlnx,zynq-periph-clock";

		clocks = <&iopll &armpll &ddrpll>;

		reg = <0x154>;

		clock-output-names = "uart0_ref_clk",

				     "uart1_ref_clk";

	};

	bool "Xilinx Zynq ARM Cortex A9 Platform"

	select ARM_AMBA

	select ARM_GIC

	select CLKDEV_LOOKUP

	select COMMON_CLK

	select CPU_V7

	select GENERIC_CLOCKEVENTS

	select ICST

		  their output to UART1 serial port on DaVinci TNETV107X

		  devices.

	config DEBUG_ZYNQ_UART0

		bool "Kernel low-level debugging on Xilinx Zynq using UART0"

		depends on ARCH_ZYNQ

		help

		  Say Y here if you want the debug print routines to direct

		  their output to UART0 on the Zynq platform.

	config DEBUG_ZYNQ_UART1

		bool "Kernel low-level debugging on Xilinx Zynq using UART1"

		depends on ARCH_ZYNQ

		help

		  Say Y here if you want the debug print routines to direct

		  their output to UART1 on the Zynq platform.

		  If you have a ZC702 board and want early boot messages to

		  appear on the USB serial adaptor, select this option.

	config DEBUG_DC21285_PORT

		bool "Kernel low-level debugging messages via footbridge serial port"

		depends on FOOTBRIDGE

# by CONFIG_* macro name.

plat-$(CONFIG_ARCH_OMAP)	+= omap

plat-$(CONFIG_ARCH_S3C64XX)	+= samsung

plat-$(CONFIG_ARCH_ZYNQ)	+= versatile

plat-$(CONFIG_PLAT_IOP)		+= iop

plat-$(CONFIG_PLAT_NOMADIK)	+= nomadik

plat-$(CONFIG_PLAT_ORION)	+= orion

dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \

	wm8505-ref.dtb \

	wm8650-mid.dtb

dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb

endif