Commit 8e3747be authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Will Deacon
Browse files

arm64: Introduce ID_ISAR6 CPU register 



This adds basic building blocks required for ID_ISAR6 CPU register which
identifies support for various instruction implementation on AArch32 state.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-kernel@vger.kernel.org
Cc: kvmarm@lists.cs.columbia.edu
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
[will: Ensure SPECRES is treated the same as on A64]
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent d4209d8b

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ struct cpuinfo_arm64 { 
	u32		reg_id_isar3;

	u32		reg_id_isar4;

	u32		reg_id_isar5;

	u32		reg_id_isar6;

	u32		reg_id_mmfr0;

	u32		reg_id_mmfr1;

	u32		reg_id_mmfr2;

arch/arm64/include/asm/sysreg.h

+9 −0
Original line number Diff line number Diff line
@@ -146,6 +146,7 @@ 
#define SYS_ID_ISAR4_EL1		sys_reg(3, 0, 0, 2, 4)

#define SYS_ID_ISAR5_EL1		sys_reg(3, 0, 0, 2, 5)

#define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)

#define SYS_ID_ISAR6_EL1		sys_reg(3, 0, 0, 2, 7)



#define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)

#define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)
@@ -691,6 +692,14 @@ 
#define ID_ISAR5_AES_SHIFT		4

#define ID_ISAR5_SEVL_SHIFT		0



#define ID_ISAR6_I8MM_SHIFT		24

#define ID_ISAR6_BF16_SHIFT		20

#define ID_ISAR6_SPECRES_SHIFT		16

#define ID_ISAR6_SB_SHIFT		12

#define ID_ISAR6_FHM_SHIFT		8

#define ID_ISAR6_DP_SHIFT		4

#define ID_ISAR6_JSCVT_SHIFT		0



#define MVFR0_FPROUND_SHIFT		28

#define MVFR0_FPSHVEC_SHIFT		24

#define MVFR0_FPSQRT_SHIFT		20

arch/arm64/kernel/cpufeature.c

+16 −0
Original line number Diff line number Diff line
@@ -325,6 +325,17 @@ static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 
	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_isar6[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_pfr0[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),		/* State3 */

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),		/* State2 */
@@ -408,6 +419,7 @@ static const struct __ftr_reg_entry { 
	ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),

	ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),

	ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),



	/* Op1 = 0, CRn = 0, CRm = 3 */

	ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
@@ -612,6 +624,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) 
		init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);

		init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);

		init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);

		init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);

		init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);

		init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);

		init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
@@ -765,6 +778,8 @@ void update_cpu_features(int cpu, 
					info->reg_id_isar4, boot->reg_id_isar4);

		taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,

					info->reg_id_isar5, boot->reg_id_isar5);

		taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,

					info->reg_id_isar6, boot->reg_id_isar6);



		/*

		 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
@@ -843,6 +858,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id) 
	read_sysreg_case(SYS_ID_ISAR3_EL1);

	read_sysreg_case(SYS_ID_ISAR4_EL1);

	read_sysreg_case(SYS_ID_ISAR5_EL1);

	read_sysreg_case(SYS_ID_ISAR6_EL1);

	read_sysreg_case(SYS_MVFR0_EL1);

	read_sysreg_case(SYS_MVFR1_EL1);

	read_sysreg_case(SYS_MVFR2_EL1);

arch/arm64/kernel/cpuinfo.c

+1 −0
Original line number Diff line number Diff line
@@ -367,6 +367,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
		info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);

		info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);

		info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);

		info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);

		info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);

		info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);

		info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);

arch/arm64/kvm/sys_regs.c

+1 −1
Original line number Diff line number Diff line
@@ -1424,7 +1424,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	ID_SANITISED(ID_ISAR4_EL1),

	ID_SANITISED(ID_ISAR5_EL1),

	ID_SANITISED(ID_MMFR4_EL1),

	ID_UNALLOCATED(2,7),

	ID_SANITISED(ID_ISAR6_EL1),



	/* CRm=3 */

	ID_SANITISED(MVFR0_EL1),

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