Commit d4209d8b authored by Steven Price's avatar Steven Price Committed by Will Deacon
Browse files

arm64: cpufeature: Export matrix and other features to userspace 



Export the features introduced as part of ARMv8.6 exposed in the
ID_AA64ISAR1_EL1 and ID_AA64ZFR0_EL1 registers. This introduces the
Matrix features (ARMv8.2-I8MM, ARMv8.2-F64MM and ARMv8.2-F32MM) along
with BFloat16 (Armv8.2-BF16), speculation invalidation (SPECRES) and
Data Gathering Hint (ARMv8.0-DGH).

Signed-off-by: default avatarJulien Grall <julien.grall@arm.com>
[Added other features in those registers]
Signed-off-by: default avatarSteven Price <steven.price@arm.com>
[will: Don't advertise SPECRES to userspace]
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 46cf053e

Documentation/arm64/cpu-feature-registers.rst

+14 −0
Original line number Diff line number Diff line
@@ -200,6 +200,12 @@ infrastructure: 
     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | I8MM                         | [55-52] |    y    |

     +------------------------------+---------+---------+

     | DGH                          | [51-48] |    y    |

     +------------------------------+---------+---------+

     | BF16                         | [47-44] |    y    |

     +------------------------------+---------+---------+

     | SB                           | [39-36] |    y    |

     +------------------------------+---------+---------+

     | FRINTTS                      | [35-32] |    y    |
@@ -234,10 +240,18 @@ infrastructure: 
     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | F64MM                        | [59-56] |    y    |

     +------------------------------+---------+---------+

     | F32MM                        | [55-52] |    y    |

     +------------------------------+---------+---------+

     | I8MM                         | [47-44] |    y    |

     +------------------------------+---------+---------+

     | SM4                          | [43-40] |    y    |

     +------------------------------+---------+---------+

     | SHA3                         | [35-32] |    y    |

     +------------------------------+---------+---------+

     | BF16                         | [23-20] |    y    |

     +------------------------------+---------+---------+

     | BitPerm                      | [19-16] |    y    |

     +------------------------------+---------+---------+

     | AES                          | [7-4]   |    y    |

Documentation/arm64/elf_hwcaps.rst

+27 −0
Original line number Diff line number Diff line
@@ -204,6 +204,33 @@ HWCAP2_FRINT 


    Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.



HWCAP2_SVEI8MM



    Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.



HWCAP2_SVEF32MM



    Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.



HWCAP2_SVEF64MM



    Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.



HWCAP2_SVEBF16



    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.



HWCAP2_I8MM



    Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.



HWCAP2_BF16



    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001.



HWCAP2_DGH



    Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

arch/arm64/include/asm/hwcap.h

+7 −0
Original line number Diff line number Diff line
@@ -86,6 +86,13 @@ 
#define KERNEL_HWCAP_SVESM4		__khwcap2_feature(SVESM4)

#define KERNEL_HWCAP_FLAGM2		__khwcap2_feature(FLAGM2)

#define KERNEL_HWCAP_FRINT		__khwcap2_feature(FRINT)

#define KERNEL_HWCAP_SVEI8MM		__khwcap2_feature(SVEI8MM)

#define KERNEL_HWCAP_SVEF32MM		__khwcap2_feature(SVEF32MM)

#define KERNEL_HWCAP_SVEF64MM		__khwcap2_feature(SVEF64MM)

#define KERNEL_HWCAP_SVEBF16		__khwcap2_feature(SVEBF16)

#define KERNEL_HWCAP_I8MM		__khwcap2_feature(I8MM)

#define KERNEL_HWCAP_DGH		__khwcap2_feature(DGH)

#define KERNEL_HWCAP_BF16		__khwcap2_feature(BF16)



/*

 * This yields a mask that user programs can use to figure out what

arch/arm64/include/asm/sysreg.h

+12 −0
Original line number Diff line number Diff line
@@ -553,6 +553,10 @@ 
#define ID_AA64ISAR0_AES_SHIFT		4



/* id_aa64isar1 */

#define ID_AA64ISAR1_I8MM_SHIFT		52

#define ID_AA64ISAR1_DGH_SHIFT		48

#define ID_AA64ISAR1_BF16_SHIFT		44

#define ID_AA64ISAR1_SPECRES_SHIFT	40

#define ID_AA64ISAR1_SB_SHIFT		36

#define ID_AA64ISAR1_FRINTTS_SHIFT	32

#define ID_AA64ISAR1_GPI_SHIFT		28
@@ -605,12 +609,20 @@ 
#define ID_AA64PFR1_SSBS_PSTATE_INSNS	2



/* id_aa64zfr0 */

#define ID_AA64ZFR0_F64MM_SHIFT		56

#define ID_AA64ZFR0_F32MM_SHIFT		52

#define ID_AA64ZFR0_I8MM_SHIFT		44

#define ID_AA64ZFR0_SM4_SHIFT		40

#define ID_AA64ZFR0_SHA3_SHIFT		32

#define ID_AA64ZFR0_BF16_SHIFT		20

#define ID_AA64ZFR0_BITPERM_SHIFT	16

#define ID_AA64ZFR0_AES_SHIFT		4

#define ID_AA64ZFR0_SVEVER_SHIFT	0



#define ID_AA64ZFR0_F64MM		0x1

#define ID_AA64ZFR0_F32MM		0x1

#define ID_AA64ZFR0_I8MM		0x1

#define ID_AA64ZFR0_BF16		0x1

#define ID_AA64ZFR0_SM4			0x1

#define ID_AA64ZFR0_SHA3		0x1

#define ID_AA64ZFR0_BITPERM		0x1

arch/arm64/include/uapi/asm/hwcap.h

+7 −0
Original line number Diff line number Diff line
@@ -65,5 +65,12 @@ 
#define HWCAP2_SVESM4		(1 << 6)

#define HWCAP2_FLAGM2		(1 << 7)

#define HWCAP2_FRINT		(1 << 8)

#define HWCAP2_SVEI8MM		(1 << 9)

#define HWCAP2_SVEF32MM		(1 << 10)

#define HWCAP2_SVEF64MM		(1 << 11)

#define HWCAP2_SVEBF16		(1 << 12)

#define HWCAP2_I8MM		(1 << 13)

#define HWCAP2_BF16		(1 << 14)

#define HWCAP2_DGH		(1 << 15)



#endif /* _UAPI__ASM_HWCAP_H */

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