Commit 8c7e96d3 authored by Vidya Sagar's avatar Vidya Sagar Committed by Lorenzo Pieralisi
Browse files

PCI: Disable MSI for Tegra root ports 



Tegra PCIe rootports don't generate MSI interrupts for PME and AER events.
Since PCIe spec (Ref: r4.0 sec 7.7.1.2 and 7.7.2.2) doesn't support using
a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid root ports
service drivers registering their respective ISRs with MSI interrupt and
to let only INTx be used for all events.

Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarThierry Reding <treding@nvidia.com>
parent 448d5a55

drivers/pci/quirks.c

+53 −0
Original line number Diff line number Diff line
@@ -2592,6 +2592,59 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 
			PCI_DEVICE_ID_NVIDIA_NVENET_15,

			nvenet_msi_disable);



/*

 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,

 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't

 * generate MSI interrupts for PME and AER events instead only INTx interrupts

 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts

 * for other events, since PCIe specificiation doesn't support using a mix of

 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port

 * service drivers registering their respective ISRs for MSIs.

 */

static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)

{

	dev->no_msi = 1;

}

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);

DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,

			      PCI_CLASS_BRIDGE_PCI, 8,

			      pci_quirk_nvidia_tegra_disable_rp_msi);



/*

 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing

 * config register.  This register controls the routing of legacy

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