PCI: Add #defines for some of PCIe spec r4.0 features

#define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */

#define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */

#define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */

#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PTM

#define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */

#define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */

#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PL_16GT

#define PCI_EXT_CAP_DSN_SIZEOF	12

#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40

#define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE	0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */

#define PCI_L1SS_CTL2		0x0c	/* Control 2 Register */

/* Data Link Feature */

#define PCI_DLF_CAP		0x04	/* Capabilities Register */

#define  PCI_DLF_EXCHANGE_ENABLE	0x80000000  /* Data Link Feature Exchange Enable */

/* Physical Layer 16.0 GT/s */

#define PCI_PL_16GT_LE_CTRL	0x20	/* Lane Equalization Control Register */

#define  PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK		0x0000000F

#define  PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK		0x000000F0

#define  PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT	4

#endif /* LINUX_PCI_REGS_H */