Docs/EDID: Calculate CRC while building the code (8bed5a5c) · Commits · 戴 / test

The previous version made it necessary to first generate an EDID data set without correct CRC and then to fix the CRC in a second step. This patch adds the CRC calculation to the makefile in such a way that a correct EDID data set is generated in a single build step. Successfully tested with all existing and a couple of new data sets. Signed-off-by:

Christoph Niedermaier <cniedermaier@dh-electronics.de> Reviewed-by:

Carsten Emde <C.Emde@osadl.org> Signed-off-by:

Jonathan Corbet <corbet@lwn.net>

Documentation/EDID/1024x768.S

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		@@ -39,6 +39,5 @@
		#define ESTABLISHED_TIMING2_BITS 0x08 /* Bit 3 -> 1024x768 @60 Hz */
		#define HSYNC_POL 0
		#define VSYNC_POL 0
		#define CRC 0x55

		#include "edid.S"

Documentation/EDID/1280x1024.S

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Original line number	Diff line number	Diff line
		@@ -39,6 +39,5 @@
		/* No ESTABLISHED_TIMINGx_BITS */
		#define HSYNC_POL 1
		#define VSYNC_POL 1
		#define CRC 0xa0

		#include "edid.S"

Documentation/EDID/1600x1200.S

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Original line number	Diff line number	Diff line
		@@ -39,6 +39,5 @@
		/* No ESTABLISHED_TIMINGx_BITS */
		#define HSYNC_POL 1
		#define VSYNC_POL 1
		#define CRC 0x9d

		#include "edid.S"

Documentation/EDID/1680x1050.S

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Original line number	Diff line number	Diff line
		@@ -39,6 +39,5 @@
		/* No ESTABLISHED_TIMINGx_BITS */
		#define HSYNC_POL 1
		#define VSYNC_POL 1
		#define CRC 0x26

		#include "edid.S"

Documentation/EDID/1920x1080.S

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Original line number	Diff line number	Diff line
		@@ -39,6 +39,5 @@
		/* No ESTABLISHED_TIMINGx_BITS */
		#define HSYNC_POL 1
		#define VSYNC_POL 1
		#define CRC 0x05

		#include "edid.S"

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