Commit 8b1935e6 authored by Guennadi Liakhovetski's avatar Guennadi Liakhovetski Committed by Paul Mundt
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dmaengine: shdma: separate DMA headers. 



Separate SH DMA headers into ones, commonly used by both drivers, and ones,
specific to each of them. This will make the future development of the
dmaengine driver easier.

Signed-off-by: default avatarGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 027811b9

arch/sh/include/asm/dma-register.h

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+51 −0
Original line number Diff line number Diff line 
/*

 * Common header for the legacy SH DMA driver and the new dmaengine driver

 *

 * extracted from arch/sh/include/asm/dma-sh.h:

 *

 * Copyright (C) 2000  Takashi YOSHII

 * Copyright (C) 2003  Paul Mundt

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#ifndef DMA_REGISTER_H

#define DMA_REGISTER_H



/* DMA register */

#define SAR	0x00

#define DAR	0x04

#define TCR	0x08

#define CHCR	0x0C

#define DMAOR	0x40



/* DMAOR definitions */

#define DMAOR_AE	0x00000004

#define DMAOR_NMIF	0x00000002

#define DMAOR_DME	0x00000001



/* Definitions for the SuperH DMAC */

#define REQ_L	0x00000000

#define REQ_E	0x00080000

#define RACK_H	0x00000000

#define RACK_L	0x00040000

#define ACK_R	0x00000000

#define ACK_W	0x00020000

#define ACK_H	0x00000000

#define ACK_L	0x00010000

#define DM_INC	0x00004000

#define DM_DEC	0x00008000

#define DM_FIX	0x0000c000

#define SM_INC	0x00001000

#define SM_DEC	0x00002000

#define SM_FIX	0x00003000

#define RS_IN	0x00000200

#define RS_OUT	0x00000300

#define TS_BLK	0x00000040

#define TM_BUR	0x00000020

#define CHCR_DE	0x00000001

#define CHCR_TE	0x00000002

#define CHCR_IE	0x00000004



#endif

arch/sh/include/asm/dma-sh.h

+2 −93
Original line number Diff line number Diff line
@@ -11,7 +11,8 @@ 
#ifndef __DMA_SH_H

#define __DMA_SH_H



#include <asm/dma.h>

#include <asm/dma-register.h>

#include <cpu/dma-register.h>

#include <cpu/dma.h>



/* DMAOR contorl: The DMAOR access size is different by CPU.*/
@@ -53,34 +54,6 @@ static int dmte_irq_map[] __maybe_unused = { 
#endif

};



/* Definitions for the SuperH DMAC */

#define REQ_L	0x00000000

#define REQ_E	0x00080000

#define RACK_H	0x00000000

#define RACK_L	0x00040000

#define ACK_R	0x00000000

#define ACK_W	0x00020000

#define ACK_H	0x00000000

#define ACK_L	0x00010000

#define DM_INC	0x00004000

#define DM_DEC	0x00008000

#define DM_FIX	0x0000c000

#define SM_INC	0x00001000

#define SM_DEC	0x00002000

#define SM_FIX	0x00003000

#define RS_IN	0x00000200

#define RS_OUT	0x00000300

#define TS_BLK	0x00000040

#define TM_BUR	0x00000020

#define CHCR_DE 0x00000001

#define CHCR_TE 0x00000002

#define CHCR_IE 0x00000004



/* DMAOR definitions */

#define DMAOR_AE	0x00000004

#define DMAOR_NMIF	0x00000002

#define DMAOR_DME	0x00000001



/*

 * Define the default configuration for dual address memory-memory transfer.

 * The 0x400 value represents auto-request, external->external.
@@ -111,68 +84,4 @@ static u32 dma_base_addr[] __maybe_unused = { 
#endif

};



/* DMA register */

#define SAR     0x00

#define DAR     0x04

#define TCR     0x08

#define CHCR    0x0C

#define DMAOR	0x40



/*

 * for dma engine

 *

 * SuperH DMA mode

 */

#define SHDMA_MIX_IRQ	(1 << 1)

#define SHDMA_DMAOR1	(1 << 2)

#define SHDMA_DMAE1	(1 << 3)



enum sh_dmae_slave_chan_id {

	SHDMA_SLAVE_SCIF0_TX,

	SHDMA_SLAVE_SCIF0_RX,

	SHDMA_SLAVE_SCIF1_TX,

	SHDMA_SLAVE_SCIF1_RX,

	SHDMA_SLAVE_SCIF2_TX,

	SHDMA_SLAVE_SCIF2_RX,

	SHDMA_SLAVE_SCIF3_TX,

	SHDMA_SLAVE_SCIF3_RX,

	SHDMA_SLAVE_SCIF4_TX,

	SHDMA_SLAVE_SCIF4_RX,

	SHDMA_SLAVE_SCIF5_TX,

	SHDMA_SLAVE_SCIF5_RX,

	SHDMA_SLAVE_SIUA_TX,

	SHDMA_SLAVE_SIUA_RX,

	SHDMA_SLAVE_SIUB_TX,

	SHDMA_SLAVE_SIUB_RX,

	SHDMA_SLAVE_NUMBER,	/* Must stay last */

};



struct sh_dmae_slave_config {

	enum sh_dmae_slave_chan_id	slave_id;

	dma_addr_t			addr;

	u32				chcr;

	char				mid_rid;

};



struct sh_dmae_channel {

	unsigned int	offset;

	unsigned int	dmars;

	unsigned int	dmars_bit;

};



struct sh_dmae_pdata {

	struct sh_dmae_slave_config *slave;

	int slave_num;

	struct sh_dmae_channel *channel;

	int channel_num;

};



struct device;



struct sh_dmae_slave {

	enum sh_dmae_slave_chan_id	slave_id; /* Set by the platform */

	struct device			*dma_dev; /* Set by the platform */

	struct sh_dmae_slave_config	*config;  /* Set by the driver */

};



#endif /* __DMA_SH_H */

arch/sh/include/asm/dmaengine.h

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/*

 * Header for the new SH dmaengine driver

 *

 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#ifndef ASM_DMAENGINE_H

#define ASM_DMAENGINE_H



#include <asm/dma-register.h>



#define SH_DMAC_MAX_CHANNELS	6



enum sh_dmae_slave_chan_id {

	SHDMA_SLAVE_SCIF0_TX,

	SHDMA_SLAVE_SCIF0_RX,

	SHDMA_SLAVE_SCIF1_TX,

	SHDMA_SLAVE_SCIF1_RX,

	SHDMA_SLAVE_SCIF2_TX,

	SHDMA_SLAVE_SCIF2_RX,

	SHDMA_SLAVE_SCIF3_TX,

	SHDMA_SLAVE_SCIF3_RX,

	SHDMA_SLAVE_SCIF4_TX,

	SHDMA_SLAVE_SCIF4_RX,

	SHDMA_SLAVE_SCIF5_TX,

	SHDMA_SLAVE_SCIF5_RX,

	SHDMA_SLAVE_SIUA_TX,

	SHDMA_SLAVE_SIUA_RX,

	SHDMA_SLAVE_SIUB_TX,

	SHDMA_SLAVE_SIUB_RX,

	SHDMA_SLAVE_NUMBER,	/* Must stay last */

};



struct sh_dmae_slave_config {

	enum sh_dmae_slave_chan_id	slave_id;

	dma_addr_t			addr;

	u32				chcr;

	char				mid_rid;

};



struct sh_dmae_channel {

	unsigned int	offset;

	unsigned int	dmars;

	unsigned int	dmars_bit;

};



struct sh_dmae_pdata {

	struct sh_dmae_slave_config *slave;

	int slave_num;

	struct sh_dmae_channel *channel;

	int channel_num;

	unsigned int ts_low_shift;

	unsigned int ts_low_mask;

	unsigned int ts_high_shift;

	unsigned int ts_high_mask;

	unsigned int *ts_shift;

	int ts_shift_num;

	u16 dmaor_init;

};



struct device;



/* Used by slave DMA clients to request DMA to/from a specific peripheral */

struct sh_dmae_slave {

	enum sh_dmae_slave_chan_id	slave_id; /* Set by the platform */

	struct device			*dma_dev; /* Set by the platform */

	struct sh_dmae_slave_config	*config;  /* Set by the driver */

};



#endif

arch/sh/include/asm/siu.h

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
#ifndef ASM_SIU_H

#define ASM_SIU_H



#include <asm/dma-sh.h>

#include <asm/dmaengine.h>



struct device;

arch/sh/include/cpu-sh3/cpu/dma-register.h

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Original line number Diff line number Diff line 
/*

 * SH3 CPU-specific DMA definitions, used by both DMA drivers

 *

 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#ifndef CPU_DMA_REGISTER_H

#define CPU_DMA_REGISTER_H



#define CHCR_TS_LOW_MASK	0x18

#define CHCR_TS_LOW_SHIFT	3

#define CHCR_TS_HIGH_MASK	0

#define CHCR_TS_HIGH_SHIFT	0



#define DMAOR_INIT	DMAOR_DME



/*

 * The SuperH DMAC supports a number of transmit sizes, we list them here,

 * with their respective values as they appear in the CHCR registers.

 */

enum {

	XMIT_SZ_8BIT,

	XMIT_SZ_16BIT,

	XMIT_SZ_32BIT,

	XMIT_SZ_128BIT,

};



/* log2(size / 8) - used to calculate number of transfers */

#define TS_SHIFT {			\

	[XMIT_SZ_8BIT]		= 0,	\

	[XMIT_SZ_16BIT]		= 1,	\

	[XMIT_SZ_32BIT]		= 2,	\

	[XMIT_SZ_128BIT]	= 4,	\

}



#define TS_INDEX2VAL(i)	(((i) & 3) << CHCR_TS_LOW_SHIFT)



#endif

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