Commit 89eecd93 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
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powerpc/8xx: Use SPRN_SPRG_SCRATCH2 in DTLB miss exception



Use SPRN_SPRG_SCRATCH2 in DTLB miss exception instead of DAR
in order to be similar to ITLB miss exception.

This also simplifies mpc8xx_pmu_del()

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/e3cc8f023ef40e1e8ae144e4dd1330a5ff022528.1606231483.git.christophe.leroy@csgroup.eu
parent a314ea5a
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+4 −5
Original line number Diff line number Diff line
@@ -247,7 +247,7 @@ InstructionTLBMiss:

	. = 0x1200
DataStoreTLBMiss:
	mtspr	SPRN_DAR, r10
	mtspr	SPRN_SPRG_SCRATCH2, r10
	mtspr	SPRN_M_TW, r11
	mfcr	r11

@@ -286,11 +286,11 @@ DataStoreTLBMiss:
	li	r11, RPN_PATTERN
	rlwimi	r10, r11, 0, 24, 27	/* Set 24-27 */
	mtspr	SPRN_MD_RPN, r10	/* Update TLB entry */
	mtspr	SPRN_DAR, r11		/* Tag DAR */

	/* Restore registers */

0:	mfspr	r10, SPRN_DAR
	mtspr	SPRN_DAR, r11	/* Tag DAR */
0:	mfspr	r10, SPRN_SPRG_SCRATCH2
	mfspr	r11, SPRN_M_TW
	rfi
	patch_site	0b, patch__dtlbmiss_exit_1
@@ -300,8 +300,7 @@ DataStoreTLBMiss:
0:	lwz	r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
	addi	r10, r10, 1
	stw	r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
	mfspr	r10, SPRN_DAR
	mtspr	SPRN_DAR, r11	/* Tag DAR */
	mfspr	r10, SPRN_SPRG_SCRATCH2
	mfspr	r11, SPRN_M_TW
	rfi
#endif
+7 −12
Original line number Diff line number Diff line
@@ -153,6 +153,11 @@ static void mpc8xx_pmu_read(struct perf_event *event)

static void mpc8xx_pmu_del(struct perf_event *event, int flags)
{
	struct ppc_inst insn;

	/* mfspr r10, SPRN_SPRG_SCRATCH2 */
	insn = ppc_inst(PPC_INST_MFSPR | __PPC_RS(R10) | __PPC_SPR(SPRN_SPRG_SCRATCH2));

	mpc8xx_pmu_read(event);

	/* If it was the last user, stop counting to avoid useles overhead */
@@ -164,22 +169,12 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags)
			mtspr(SPRN_ICTRL, 7);
		break;
	case PERF_8xx_ID_ITLB_LOAD_MISS:
		if (atomic_dec_return(&itlb_miss_ref) == 0) {
			/* mfspr r10, SPRN_SPRG_SCRATCH2 */
			struct ppc_inst insn = ppc_inst(PPC_INST_MFSPR | __PPC_RS(R10) |
					    __PPC_SPR(SPRN_SPRG_SCRATCH2));

		if (atomic_dec_return(&itlb_miss_ref) == 0)
			patch_instruction_site(&patch__itlbmiss_exit_1, insn);
		}
		break;
	case PERF_8xx_ID_DTLB_LOAD_MISS:
		if (atomic_dec_return(&dtlb_miss_ref) == 0) {
			/* mfspr r10, SPRN_DAR */
			struct ppc_inst insn = ppc_inst(PPC_INST_MFSPR | __PPC_RS(R10) |
					    __PPC_SPR(SPRN_DAR));

		if (atomic_dec_return(&dtlb_miss_ref) == 0)
			patch_instruction_site(&patch__dtlbmiss_exit_1, insn);
		}
		break;
	}
}