Commit a314ea5a authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/8xx: Use SPRN_SPRG_SCRATCH2 in ITLB miss exception 



In order to re-enable MMU earlier, ensure ITLB miss exception
cannot clobber SPRN_SPRG_SCRATCH0 and SPRN_SPRG_SCRATCH1.
Do so by using SPRN_SPRG_SCRATCH2 and SPRN_M_TW instead, like
the DTLB miss exception.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/abc78e8e9577d473691ebb9996c6413b37bfd9ca.1606231483.git.christophe.leroy@csgroup.eu
parent 576e02bb

arch/powerpc/kernel/head_8xx.S

+6 −6
Original line number Diff line number Diff line
@@ -190,8 +190,8 @@ SystemCall: 
#endif



InstructionTLBMiss:

	mtspr	SPRN_SPRG_SCRATCH0, r10

	mtspr	SPRN_SPRG_SCRATCH1, r11

	mtspr	SPRN_SPRG_SCRATCH2, r10

	mtspr	SPRN_M_TW, r11



	/* If we are faulting a kernel address, we have to use the

	 * kernel page tables.
@@ -230,8 +230,8 @@ InstructionTLBMiss: 
	mtspr	SPRN_MI_RPN, r10	/* Update TLB entry */



	/* Restore registers */

0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

0:	mfspr	r10, SPRN_SPRG_SCRATCH2

	mfspr	r11, SPRN_M_TW

	rfi

	patch_site	0b, patch__itlbmiss_exit_1
@@ -240,8 +240,8 @@ InstructionTLBMiss: 
0:	lwz	r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)

	addi	r10, r10, 1

	stw	r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)

	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	mfspr	r10, SPRN_SPRG_SCRATCH2

	mfspr	r11, SPRN_M_TW

	rfi

#endif

arch/powerpc/perf/8xx-pmu.c

+2 −2
Original line number Diff line number Diff line
@@ -165,9 +165,9 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags) 
		break;

	case PERF_8xx_ID_ITLB_LOAD_MISS:

		if (atomic_dec_return(&itlb_miss_ref) == 0) {

			/* mfspr r10, SPRN_SPRG_SCRATCH0 */

			/* mfspr r10, SPRN_SPRG_SCRATCH2 */

			struct ppc_inst insn = ppc_inst(PPC_INST_MFSPR | __PPC_RS(R10) |

					    __PPC_SPR(SPRN_SPRG_SCRATCH0));

					    __PPC_SPR(SPRN_SPRG_SCRATCH2));



			patch_instruction_site(&patch__itlbmiss_exit_1, insn);

		}

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