ath5k: Update RF Buffer handling

#define AR5K_INI_VAL_XR			0

#define AR5K_INI_VAL_MAX		5

#define AR5K_RF5111_INI_RF_MAX_BANKS	AR5K_MAX_RF_BANKS

#define AR5K_RF5112_INI_RF_MAX_BANKS	AR5K_MAX_RF_BANKS

/* Used for BSSID etc manipulation */

#define AR5K_LOW_ID(_a)(				\

(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24	\

#define AR5K_SREV_PHY_5211	0x30

#define AR5K_SREV_PHY_5212	0x41

#define	AR5K_SREV_PHY_5212A	0x42

#define AR5K_SREV_PHY_2112B	0x43

#define AR5K_SREV_PHY_2413	0x45

#define AR5K_SREV_PHY_5413	0x61

	u32			ah_txq_isr;

	u32			*ah_rf_banks;

	size_t			ah_rf_banks_size;

	size_t			ah_rf_regs_count;

	struct ath5k_gain	ah_gain;

	u32			ah_offset[AR5K_MAX_RF_BANKS];

	u8			ah_offset[AR5K_MAX_RF_BANKS];

	struct {

		u16		txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];

extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);

/* Initialize RF */

extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int mode);

extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,

				struct ieee80211_channel *channel,

				unsigned int mode);

extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);

extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);

extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);

/*

 * RF Buffer register

 *

 * There are some special control registers on the RF chip

 * that hold various operation settings related mostly to

 * the analog parts (channel, gain adjustment etc).

 *

 * We don't write on those registers directly but

 * we send a data packet on the buffer register and

 * then write on another special register to notify hw

 * to apply the settings. This is done so that control registers

 * can be dynamicaly programmed during operation and the settings

 * are applied faster on the hw.

 *

 * We sent such data packets during rf initialization and channel change

 * through ath5k_hw_rf*_rfregs and ath5k_hw_rf*_channel functions.

 *

 * The data packets we send during initializadion are inside ath5k_ini_rf

 * struct (see ath5k_hw.h) and each one is related to an "rf register bank".

 * We use *rfregs functions to modify them  acording to current operation

 * mode and eeprom values and pass them all together to the chip.

 *

 * It's obvious from the code that 0x989c is the buffer register but

 * for the other special registers that we write to after sending each

 * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers

 * for now. It's interesting that they are also used for some other operations.

 *

 * Also check out hw.h and U.S. Patent 6677779 B1 (about buffer

 * registers and control registers):

 *

 * http://www.google.com/patents?id=qNURAAAAEBAJ

 */

#define AR5K_RF_BUFFER			0x989c

		/*

		 * Write RF registers

		 */

		ret = ath5k_hw_rfregs(ah, channel, mode);

		ret = ath5k_hw_rfregs_init(ah, channel, mode);

		if (ret)

			return ret;