Commit 863bae1f authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-5.10' of... 

Merge tag 'irqchip-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates from Marc Zyngier:

 Core changes:

  - Allow irq retriggering to follow a hierarchy
  - Allow interrupt hierarchies to be trimmed at allocation time
  - Allow interrupts to be hidden from /proc/interrupts (IPIs)
  - Introduce stub for set_handle_irq() when !GENERIC_IRQ_MULTI_HANDLER
  - New per-cpu IPI handling flow

 Architecture changes:
  - Move arm/arm64 IPI handling to the core interrupt code, removing
    the home brewed accounting

 Driver updates:
 - New driver for the MStar (and more recently Mediatek) platforms
 - New driver for the Actions Owl SIRQ controller
 - New driver for the TI PRUSS infrastructure
 - Wake-up support for the Qualcomm PDC controller
 - Primary interrupt controller support for the Designware APB ICTL
 - Convert the IPI code for GIC, GICv3, hip04, armada-270-xp and bcm2836
   to using standard interrupts
 - Improve GICv3 pseudo-NMI support to deal with both non-secure and secure
   priorities on arm64
 - Convert the GIC/GICv3 drivers to using HW-based irq retrigger
 - A sprinkling of dev_err_probe() conversion
 - A set of NVIDIA Tegra fixes for interrupt hierarchy corruption
 - A reset fix for the Loongson HTVEC driver
 - A couple of error handling fixes in the TI SCI drivers
parents cdabce2e 63ea38a4

Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml

0 → 100644
+65 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Actions Semi Owl SoCs SIRQ interrupt controller



maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>



description: |

  This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700

  and S900) and provides support for handling up to 3 external interrupt lines.



properties:

  compatible:

    enum:

      - actions,s500-sirq

      - actions,s700-sirq

      - actions,s900-sirq



  reg:

    maxItems: 1



  interrupt-controller: true



  '#interrupt-cells':

    const: 2

    description:

      The first cell is the input IRQ number, between 0 and 2, while the second

      cell is the trigger type as defined in interrupt.txt in this directory.



  'interrupts':

    description: |

      Contains the GIC SPI IRQs mapped to the external interrupt lines.

      They shall be specified sequentially from output 0 to 2.

    minItems: 3

    maxItems: 3



required:

  - compatible

  - reg

  - interrupt-controller

  - '#interrupt-cells'

  - 'interrupts'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    sirq: interrupt-controller@b01b0200 {

      compatible = "actions,s500-sirq";

      reg = <0xb01b0200 0x4>;

      interrupt-controller;

      #interrupt-cells = <2>;

      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */

                   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */

                   <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */

    };



...

Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml

0 → 100644
+64 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MStar Interrupt Controller



maintainers:

  - Mark-PK Tsai <mark-pk.tsai@mediatek.com>



description: |+

  MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy

  interrupt controllers that routes interrupts to the GIC.



  The HW block exposes a number of interrupt controllers, each

  can support up to 64 interrupts.



properties:

  compatible:

    const: mstar,mst-intc



  interrupt-controller: true



  "#interrupt-cells":

    const: 3

    description: |

      Use the same format as specified by GIC in arm,gic.yaml.



  reg:

    maxItems: 1



  mstar,irqs-map-range:

    description: |

      The range <start, end> of parent interrupt controller's interrupt

      lines that are hardwired to mstar interrupt controller.

    $ref: /schemas/types.yaml#/definitions/uint32-matrix

    items:

      minItems: 2

      maxItems: 2



  mstar,intc-no-eoi:

    description:

      Mark this controller has no End Of Interrupt(EOI) implementation.

    type: boolean



required:

  - compatible

  - reg

  - mstar,irqs-map-range



additionalProperties: false



examples:

  - |

    mst_intc0: interrupt-controller@1f2032d0 {

      compatible = "mstar,mst-intc";

      interrupt-controller;

      #interrupt-cells = <3>;

      interrupt-parent = <&gic>;

      reg = <0x1f2032d0 0x30>;

      mstar,irqs-map-range = <0 63>;

    };

...

Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt

+13 −1
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ Synopsys DesignWare APB interrupt controller (dw_apb_ictl) 


Synopsys DesignWare provides interrupt controller IP for APB known as

dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with

APB bus, e.g. Marvell Armada 1500.

APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt

controller in some SoCs, e.g. Hisilicon SD5203.



Required properties:

- compatible: shall be "snps,dw-apb-ictl"
@@ -10,6 +11,8 @@ Required properties: 
  region starting with ENABLE_LOW register

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1



Additional required property when it's used as secondary interrupt controller:

- interrupts: interrupt reference to primary interrupt controller



The interrupt sources map to the corresponding bits in the interrupt
@@ -21,6 +24,7 @@ registers, i.e. 
- (optional) fast interrupts start at 64.



Example:

	/* dw_apb_ictl is used as secondary interrupt controller */

	aic: interrupt-controller@3000 {

		compatible = "snps,dw-apb-ictl";

		reg = <0x3000 0xc00>;
@@ -29,3 +33,11 @@ Example: 
		interrupt-parent = <&gic>;

		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

	};



	/* dw_apb_ictl is used as primary interrupt controller */

	vic: interrupt-controller@10130000 {

		compatible = "snps,dw-apb-ictl";

		reg = <0x10130000 0x1000>;

		interrupt-controller;

		#interrupt-cells = <1>;

	};

Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml

0 → 100644
+158 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: TI PRU-ICSS Local Interrupt Controller



maintainers:

  - Suman Anna <s-anna@ti.com>



description: |

  Each PRU-ICSS has a single interrupt controller instance that is common

  to all the PRU cores. Most interrupt controllers can route 64 input events

  which are then mapped to 10 possible output interrupts through two levels

  of mapping. The input events can be triggered by either the PRUs and/or

  various other PRUSS internal and external peripherals. The first 2 output

  interrupts (0, 1) are fed exclusively to the internal PRU cores, with the

  remaining 8 (2 through 9) connected to external interrupt controllers

  including the MPU and/or other PRUSS instances, DSPs or devices.



  The property "ti,irqs-reserved" is used for denoting the connection

  differences on the output interrupts 2 through 9. If this property is not

  defined, it implies that all the PRUSS INTC output interrupts 2 through 9

  (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt

  controller.



  The K3 family of SoCs can handle 160 input events that can be mapped to 20

  different possible output interrupts. The additional output interrupts (10

  through 19) are connected to new sub-modules within the ICSSG instances.



  This interrupt-controller node should be defined as a child node of the

  corresponding PRUSS node. The node should be named "interrupt-controller".



properties:

  compatible:

    enum:

      - ti,pruss-intc

      - ti,icssg-intc

    description: |

      Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,

                              AM335x family of SoCs,

                              AM437x family of SoCs,

                              AM57xx family of SoCs

                              66AK2G family of SoCs

      Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs



  reg:

    maxItems: 1



  interrupts:

    minItems: 1

    maxItems: 8

    description: |

      All the interrupts generated towards the main host processor in the SoC.

      A shared interrupt can be skipped if the desired destination and usage is

      by a different processor/device.



  interrupt-names:

    minItems: 1

    maxItems: 8

    items:

      pattern: host_intr[0-7]

    description: |

      Should use one of the above names for each valid host event interrupt

      connected to Arm interrupt controller, the name should match the

      corresponding host event interrupt number.



  interrupt-controller: true



  "#interrupt-cells":

    const: 3

    description: |

      Client users shall use the PRU System event number (the interrupt source

      that the client is interested in) [cell 1], PRU channel [cell 2] and PRU

      host_event (target) [cell 3] as the value of the interrupts property in

      their node.  The system events can be mapped to some output host

      interrupts through 2 levels of many-to-one mapping i.e. events to channel

      mapping and channels to host interrupts so through this property entire

      mapping is provided.



  ti,irqs-reserved:

    $ref: /schemas/types.yaml#definitions/uint8

    description: |

      Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC

      output interrupts 2 through 9) that are not connected to the Arm interrupt

      controller or are shared and used by other devices or processors in the

      SoC. Define this property when any of 8 interrupts should not be handled

      by Arm interrupt controller.

        Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt

              connected to MPU

            - AM65x and J721E SoCs have "host_intr5", "host_intr6" and

              "host_intr7" interrupts connected to MPU, and other ICSSG

              instances.



required:

 - compatible

 - reg

 - interrupts

 - interrupt-names

 - interrupt-controller

 - "#interrupt-cells"



additionalProperties: false



examples:

  - |

    /* AM33xx PRU-ICSS */

    pruss: pruss@0 {

        compatible = "ti,am3356-pruss";

        reg = <0x0 0x80000>;

        #address-cells = <1>;

        #size-cells = <1>;

        ranges;



        pruss_intc: interrupt-controller@20000 {

            compatible = "ti,pruss-intc";

            reg = <0x20000 0x2000>;

            interrupts = <20 21 22 23 24 25 26 27>;

            interrupt-names = "host_intr0", "host_intr1",

                              "host_intr2", "host_intr3",

                              "host_intr4", "host_intr5",

                              "host_intr6", "host_intr7";

            interrupt-controller;

            #interrupt-cells = <3>;

        };

    };



  - |



    /* AM4376 PRU-ICSS */

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pruss@0 {

        compatible = "ti,am4376-pruss";

        reg = <0x0 0x40000>;

        #address-cells = <1>;

        #size-cells = <1>;

        ranges;



        interrupt-controller@20000 {

            compatible = "ti,pruss-intc";

            reg = <0x20000 0x2000>;

            interrupt-controller;

            #interrupt-cells = <3>;

            interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "host_intr0", "host_intr1",

                              "host_intr2", "host_intr3",

                              "host_intr4",

                              "host_intr6", "host_intr7";

            ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */

        };

    };

MAINTAINERS

+9 −0
Original line number Diff line number Diff line
@@ -1525,6 +1525,7 @@ F: Documentation/devicetree/bindings/arm/actions.yaml 
F:	Documentation/devicetree/bindings/clock/actions,owl-cmu.txt

F:	Documentation/devicetree/bindings/dma/owl-dma.txt

F:	Documentation/devicetree/bindings/i2c/i2c-owl.txt

F:	Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml

F:	Documentation/devicetree/bindings/mmc/owl-mmc.yaml

F:	Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt

F:	Documentation/devicetree/bindings/power/actions,owl-sps.txt
@@ -1536,6 +1537,7 @@ F: drivers/clk/actions/ 
F:	drivers/clocksource/timer-owl*

F:	drivers/dma/owl-dma.c

F:	drivers/i2c/busses/i2c-owl.c

F:	drivers/irqchip/irq-owl-sirq.c

F:	drivers/mmc/host/owl-mmc.c

F:	drivers/pinctrl/actions/*

F:	drivers/soc/actions/
@@ -11779,6 +11781,13 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/ 
T:	git git://linuxtv.org/anttip/media_tree.git

F:	drivers/media/usb/msi2500/













MSTAR INTERRUPT CONTROLLER DRIVER













M:	Mark-PK Tsai <mark-pk.tsai@mediatek.com>













M:	Daniel Palmer <daniel@thingy.jp>













S:	Maintained













F:	Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml













F:	drivers/irqchip/irq-mst-intc.c



























MSYSTEMS DISKONCHIP G3 MTD DRIVER















M:	Robert Jarzmik <robert.jarzmik@free.fr>















L:	linux-mtd@lists.infradead.org









































































CRA Git | Maintained and supported by SUSTech CRA and CCSE