Merge branch 'irq/mstar' into irq/irqchip-next (63ea38a4) · Commits · 戴 / test

Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: MStar Interrupt Controller

		maintainers:
		- Mark-PK Tsai <mark-pk.tsai@mediatek.com>

		description: \|+
		MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy
		interrupt controllers that routes interrupts to the GIC.

		The HW block exposes a number of interrupt controllers, each
		can support up to 64 interrupts.

		properties:
		compatible:
		const: mstar,mst-intc

		interrupt-controller: true

		"#interrupt-cells":
		const: 3
		description: \|
		Use the same format as specified by GIC in arm,gic.yaml.

		reg:
		maxItems: 1

		mstar,irqs-map-range:
		description: \|
		The range <start, end> of parent interrupt controller's interrupt
		lines that are hardwired to mstar interrupt controller.
		$ref: /schemas/types.yaml#/definitions/uint32-matrix
		items:
		minItems: 2
		maxItems: 2

		mstar,intc-no-eoi:
		description:
		Mark this controller has no End Of Interrupt(EOI) implementation.
		type: boolean

		required:
		- compatible
		- reg
		- mstar,irqs-map-range

		additionalProperties: false

		examples:
		- \|
		mst_intc0: interrupt-controller@1f2032d0 {
		compatible = "mstar,mst-intc";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0x1f2032d0 0x30>;
		mstar,irqs-map-range = <0 63>;
		};
		...

MAINTAINERS

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		@@ -11773,6 +11773,13 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/
		T: git git://linuxtv.org/anttip/media_tree.git
		F: drivers/media/usb/msi2500/

		MSTAR INTERRUPT CONTROLLER DRIVER
		M: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
		M: Daniel Palmer <daniel@thingy.jp>
		S: Maintained
		F: Documentation/devicetree/bindings/interrupt-controller/mstar,mst-intc.yaml
		F: drivers/irqchip/irq-mst-intc.c

		MSYSTEMS DISKONCHIP G3 MTD DRIVER
		M: Robert Jarzmik <robert.jarzmik@free.fr>
		L: linux-mtd@lists.infradead.org

drivers/irqchip/Kconfig

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		@@ -581,4 +581,12 @@ config LOONGSON_PCH_MSI
		help
		Support for the Loongson PCH MSI Controller.

		config MST_IRQ
		bool "MStar Interrupt Controller"
		default ARCH_MEDIATEK
		select IRQ_DOMAIN
		select IRQ_DOMAIN_HIERARCHY
		help
		Support MStar Interrupt Controller.

		endmenu

drivers/irqchip/Makefile

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		@@ -113,3 +113,4 @@ obj-$(CONFIG_LOONGSON_HTPIC) += irq-loongson-htpic.o
		obj-$(CONFIG_LOONGSON_HTVEC) += irq-loongson-htvec.o
		obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-loongson-pch-pic.o
		obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o
		obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o

drivers/irqchip/irq-mst-intc.c

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		// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
		/*
		* Copyright (c) 2020 MediaTek Inc.
		* Author Mark-PK Tsai <mark-pk.tsai@mediatek.com>
		*/
		#include <linux/interrupt.h>
		#include <linux/io.h>
		#include <linux/irq.h>
		#include <linux/irqchip.h>
		#include <linux/irqdomain.h>
		#include <linux/of.h>
		#include <linux/of_address.h>
		#include <linux/of_irq.h>
		#include <linux/slab.h>
		#include <linux/spinlock.h>

		#define INTC_MASK 0x0
		#define INTC_EOI 0x20

		struct mst_intc_chip_data {
		raw_spinlock_t lock;
		unsigned int irq_start, nr_irqs;
		void __iomem *base;
		bool no_eoi;
		};

		static void mst_set_irq(struct irq_data *d, u32 offset)
		{
		irq_hw_number_t hwirq = irqd_to_hwirq(d);
		struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
		u16 val, mask;
		unsigned long flags;

		mask = 1 << (hwirq % 16);
		offset += (hwirq / 16) * 4;

		raw_spin_lock_irqsave(&cd->lock, flags);
		val = readw_relaxed(cd->base + offset) \| mask;
		writew_relaxed(val, cd->base + offset);
		raw_spin_unlock_irqrestore(&cd->lock, flags);
		}

		static void mst_clear_irq(struct irq_data *d, u32 offset)
		{
		irq_hw_number_t hwirq = irqd_to_hwirq(d);
		struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
		u16 val, mask;
		unsigned long flags;

		mask = 1 << (hwirq % 16);
		offset += (hwirq / 16) * 4;

		raw_spin_lock_irqsave(&cd->lock, flags);
		val = readw_relaxed(cd->base + offset) & ~mask;
		writew_relaxed(val, cd->base + offset);
		raw_spin_unlock_irqrestore(&cd->lock, flags);
		}

		static void mst_intc_mask_irq(struct irq_data *d)
		{
		mst_set_irq(d, INTC_MASK);
		irq_chip_mask_parent(d);
		}

		static void mst_intc_unmask_irq(struct irq_data *d)
		{
		mst_clear_irq(d, INTC_MASK);
		irq_chip_unmask_parent(d);
		}

		static void mst_intc_eoi_irq(struct irq_data *d)
		{
		struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);

		if (!cd->no_eoi)
		mst_set_irq(d, INTC_EOI);

		irq_chip_eoi_parent(d);
		}

		static struct irq_chip mst_intc_chip = {
		.name = "mst-intc",
		.irq_mask = mst_intc_mask_irq,
		.irq_unmask = mst_intc_unmask_irq,
		.irq_eoi = mst_intc_eoi_irq,
		.irq_get_irqchip_state = irq_chip_get_parent_state,
		.irq_set_irqchip_state = irq_chip_set_parent_state,
		.irq_set_affinity = irq_chip_set_affinity_parent,
		.irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
		.irq_set_type = irq_chip_set_type_parent,
		.irq_retrigger = irq_chip_retrigger_hierarchy,
		.flags = IRQCHIP_SET_TYPE_MASKED \|
		IRQCHIP_SKIP_SET_WAKE \|
		IRQCHIP_MASK_ON_SUSPEND,
		};

		static int mst_intc_domain_translate(struct irq_domain *d,
		struct irq_fwspec *fwspec,
		unsigned long *hwirq,
		unsigned int *type)
		{
		struct mst_intc_chip_data *cd = d->host_data;

		if (is_of_node(fwspec->fwnode)) {
		if (fwspec->param_count != 3)
		return -EINVAL;

		/* No PPI should point to this domain */
		if (fwspec->param[0] != 0)
		return -EINVAL;

		if (fwspec->param[1] >= cd->nr_irqs)
		return -EINVAL;

		*hwirq = fwspec->param[1];
		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
		return 0;
		}

		return -EINVAL;
		}

		static int mst_intc_domain_alloc(struct irq_domain *domain, unsigned int virq,
		unsigned int nr_irqs, void *data)
		{
		int i;
		irq_hw_number_t hwirq;
		struct irq_fwspec parent_fwspec, *fwspec = data;
		struct mst_intc_chip_data *cd = domain->host_data;

		/* Not GIC compliant */
		if (fwspec->param_count != 3)
		return -EINVAL;

		/* No PPI should point to this domain */
		if (fwspec->param[0])
		return -EINVAL;

		hwirq = fwspec->param[1];
		for (i = 0; i < nr_irqs; i++)
		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
		&mst_intc_chip,
		domain->host_data);

		parent_fwspec = *fwspec;
		parent_fwspec.fwnode = domain->parent->fwnode;
		parent_fwspec.param[1] = cd->irq_start + hwirq;
		return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_fwspec);
		}

		static const struct irq_domain_ops mst_intc_domain_ops = {
		.translate = mst_intc_domain_translate,
		.alloc = mst_intc_domain_alloc,
		.free = irq_domain_free_irqs_common,
		};

		int __init
		mst_intc_of_init(struct device_node dn, struct device_node parent)
		{
		struct irq_domain domain, domain_parent;
		struct mst_intc_chip_data *cd;
		u32 irq_start, irq_end;

		domain_parent = irq_find_host(parent);
		if (!domain_parent) {
		pr_err("mst-intc: interrupt-parent not found\n");
		return -EINVAL;
		}

		if (of_property_read_u32_index(dn, "mstar,irqs-map-range", 0, &irq_start) \|\|
		of_property_read_u32_index(dn, "mstar,irqs-map-range", 1, &irq_end))
		return -EINVAL;

		cd = kzalloc(sizeof(*cd), GFP_KERNEL);
		if (!cd)
		return -ENOMEM;

		cd->base = of_iomap(dn, 0);
		if (!cd->base) {
		kfree(cd);
		return -ENOMEM;
		}

		cd->no_eoi = of_property_read_bool(dn, "mstar,intc-no-eoi");
		raw_spin_lock_init(&cd->lock);
		cd->irq_start = irq_start;
		cd->nr_irqs = irq_end - irq_start + 1;
		domain = irq_domain_add_hierarchy(domain_parent, 0, cd->nr_irqs, dn,
		&mst_intc_domain_ops, cd);
		if (!domain) {
		iounmap(cd->base);
		kfree(cd);
		return -ENOMEM;
		}

		return 0;
		}

		IRQCHIP_DECLARE(mst_intc, "mstar,mst-intc", mst_intc_of_init);

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