arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register (853772ba) · Commits · 戴 / test

Enable ETS, TWED, XNX and SPECSEI features bits in ID_AA64MMFR1 register as per ARM DDI 0487F.a specification. Suggested-by:

Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Link: https://lore.kernel.org/r/1593748297-1965-3-git-send-email-anshuman.khandual@arm.com Signed-off-by:

arch/arm64/include/asm/sysreg.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -737,6 +737,10 @@
		#endif

		/* id_aa64mmfr1 */
		#define ID_AA64MMFR1_ETS_SHIFT 36
		#define ID_AA64MMFR1_TWED_SHIFT 32
		#define ID_AA64MMFR1_XNX_SHIFT 28
		#define ID_AA64MMFR1_SPECSEI_SHIFT 24
		#define ID_AA64MMFR1_PAN_SHIFT 20
		#define ID_AA64MMFR1_LOR_SHIFT 16
		#define ID_AA64MMFR1_HPD_SHIFT 12

+4 −0

Original line number	Diff line number	Diff line
		@@ -315,6 +315,10 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
		};

		static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),