Commit bc67f10a authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Catalin Marinas
Browse files

arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register 



Enable EVC, FGT, EXS features bits in ID_AA64MMFR0 register as per ARM DDI
0487F.a specification.

Suggested-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Link: https://lore.kernel.org/r/1593748297-1965-2-git-send-email-anshuman.khandual@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 9ebcfadb

arch/arm64/include/asm/sysreg.h

+3 −0
Original line number Diff line number Diff line
@@ -706,6 +706,9 @@ 
#define ID_AA64ZFR0_SVEVER_SVE2		0x1



/* id_aa64mmfr0 */

#define ID_AA64MMFR0_ECV_SHIFT		60

#define ID_AA64MMFR0_FGT_SHIFT		56

#define ID_AA64MMFR0_EXS_SHIFT		44

#define ID_AA64MMFR0_TGRAN4_2_SHIFT	40

#define ID_AA64MMFR0_TGRAN64_2_SHIFT	36

#define ID_AA64MMFR0_TGRAN16_2_SHIFT	32

arch/arm64/kernel/cpufeature.c

+3 −0
Original line number Diff line number Diff line
@@ -269,6 +269,9 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 
};



static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),

	/*

	 * Page size not being supported at Stage-2 is not fatal. You

	 * just give up KVM if PAGE_SIZE isn't supported there. Go fix

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