Commit 82cac71c authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: put Navi1X umc cdr workaround in post_smu_init 



That's where the uclk dpm get enabled and then the
uclk cdr workaround can be applied.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 10144762

drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h

+0 −1
Original line number Diff line number Diff line
@@ -590,7 +590,6 @@ struct pptable_funcs { 
	int (*mode2_reset)(struct smu_context *smu);

	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);

	int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);

	int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu);

	int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);

	void (*log_thermal_throttling_event)(struct smu_context *smu);

	size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+0 −6
Original line number Diff line number Diff line
@@ -975,12 +975,6 @@ static int smu_smc_hw_setup(struct smu_context *smu) 
		return ret;

	}



	ret = smu_disable_umc_cdr_12gbps_workaround(smu);

	if (ret) {

		dev_err(adev->dev, "Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");

		return ret;

	}



	/*

	 * For Navi1X, manually switch it to AC mode as PMFW

	 * may boot it with DC mode.

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+14 −4
Original line number Diff line number Diff line
@@ -2568,6 +2568,7 @@ static int navi10_post_smu_init(struct smu_context *smu) 
	struct smu_feature *feature = &smu->smu_feature;

	struct amdgpu_device *adev = smu->adev;

	uint64_t feature_mask = 0;

	int ret = 0;



	/* For Naiv1x, enable these features only after DAL initialization */

	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
@@ -2590,9 +2591,19 @@ static int navi10_post_smu_init(struct smu_context *smu) 
		  (unsigned long *)(&feature_mask),

		  SMU_FEATURE_MAX);



	return smu_cmn_feature_update_enable_state(smu,

	ret = smu_cmn_feature_update_enable_state(smu,

						  feature_mask,

						  true);

	if (ret) {

		dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");

		return ret;

	}



	ret = navi10_disable_umc_cdr_12gbps_workaround(smu);

	if (ret)

		dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");



	return ret;

}



static const struct pptable_funcs navi10_ppt_funcs = {
@@ -2669,7 +2680,6 @@ static const struct pptable_funcs navi10_ppt_funcs = { 
	.set_default_od_settings = navi10_set_default_od_settings,

	.od_edit_dpm_table = navi10_od_edit_dpm_table,

	.run_btc = navi10_run_btc,

	.disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround,

	.set_power_source = smu_v11_0_set_power_source,

	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,

	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,

drivers/gpu/drm/amd/pm/swsmu/smu_internal.h

+0 −1
Original line number Diff line number Diff line
@@ -83,7 +83,6 @@ 
#define smu_asic_set_performance_level(smu, level)			smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)

#define smu_dump_pptable(smu)						smu_ppt_funcs(dump_pptable, 0, smu)

#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap)	smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)

#define smu_disable_umc_cdr_12gbps_workaround(smu)			smu_ppt_funcs(disable_umc_cdr_12gbps_workaround, 0, smu)

#define smu_set_power_source(smu, power_src)				smu_ppt_funcs(set_power_source, 0, smu, power_src)

#define smu_i2c_init(smu, control)					smu_ppt_funcs(i2c_init, 0, smu, control)

#define smu_i2c_fini(smu, control)					smu_ppt_funcs(i2c_fini, 0, smu, control)

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