Commit 10144762 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2) 



This is needed for Navi1X only. And it may help for display missing
or hang issue seen on some high resolution monitors.

V2: no UCLK DPM enablement for Navi10 A0 secure SKU

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4bdd4d25

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+39 −21
Original line number Diff line number Diff line
@@ -279,9 +279,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, 
				| FEATURE_MASK(FEATURE_FW_CTF_BIT)

				| FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);



	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);



	if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
@@ -291,11 +288,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, 
	if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);



	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)

				| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)

				| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);



	if (adev->pm.pp_feature & PP_ULV_MASK)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
@@ -320,19 +312,12 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, 
	if (smu->dc_controlled_by_gpio)

		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);



	/* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */

	if (is_asic_secure(smu)) {

		/* only for navi10 A0 */

		if ((adev->asic_type == CHIP_NAVI10) &&

			(adev->rev_id == 0)) {

			*(uint64_t *)feature_mask &=

					~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)

					  | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)

					  | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));

	/* DS SOCCLK enablement should be skipped for navi10 A0 secure board */

	if (is_asic_secure(smu) &&

	    (adev->asic_type == CHIP_NAVI10) &&

	    (adev->rev_id == 0))

		*(uint64_t *)feature_mask &=

				~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);

		}

	}



	return 0;

}
@@ -2578,6 +2563,38 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) 
					       NULL);

}



static int navi10_post_smu_init(struct smu_context *smu)

{

	struct smu_feature *feature = &smu->smu_feature;

	struct amdgpu_device *adev = smu->adev;

	uint64_t feature_mask = 0;



	/* For Naiv1x, enable these features only after DAL initialization */

	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)

		feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);



	/* DPM UCLK enablement should be skipped for navi10 A0 secure board */

	if (!(is_asic_secure(smu) &&

	     (adev->asic_type == CHIP_NAVI10) &&

	     (adev->rev_id == 0)) &&

	    (adev->pm.pp_feature & PP_MCLK_DPM_MASK))

		feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)

				| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)

				| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);



	if (!feature_mask)

		return 0;



	bitmap_or(feature->allowed,

		  feature->allowed,

		  (unsigned long *)(&feature_mask),

		  SMU_FEATURE_MAX);



	return smu_cmn_feature_update_enable_state(smu,

						   feature_mask,

						   true);

}



static const struct pptable_funcs navi10_ppt_funcs = {

	.get_allowed_feature_mask = navi10_get_allowed_feature_mask,

	.set_default_dpm_table = navi10_set_default_dpm_table,
@@ -2661,6 +2678,7 @@ static const struct pptable_funcs navi10_ppt_funcs = { 
	.gfx_ulv_control = smu_v11_0_gfx_ulv_control,

	.deep_sleep_control = smu_v11_0_deep_sleep_control,

	.get_fan_parameters = navi10_get_fan_parameters,

	.post_init = navi10_post_smu_init,

};



void navi10_set_ppt_funcs(struct smu_context *smu)

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

+3 −3
Original line number Diff line number Diff line
@@ -346,7 +346,7 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu, 
	return ret;

}



static int smu_cmn_feature_update_enable_state(struct smu_context *smu,

int smu_cmn_feature_update_enable_state(struct smu_context *smu,

					uint64_t feature_mask,

					bool enabled)

{

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

+4 −0
Original line number Diff line number Diff line
@@ -52,6 +52,10 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu, 
			     uint32_t *feature_mask,

			     uint32_t num);



int smu_cmn_feature_update_enable_state(struct smu_context *smu,

					uint64_t feature_mask,

					bool enabled);



int smu_cmn_feature_set_enabled(struct smu_context *smu,

				enum smu_feature_mask mask,

				bool enable);

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