Commit 821596a5 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge branch 'clockevents/4.12' of... 

Merge branch 'clockevents/4.12' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

Pull clockevents updates from Daniel Lezcano

- Provide a framework to handle errata gracefuly for arm_arch_timer (Mark
   Zyngier)

 - Clarify the DT properties for the rockchip timer and add the clocksource as
   an alternative to the bogus architected timer (Alexander Kochetkov)

 - Rename the Gemini timer to Faraday timer fttmr010 and provide a specific
   initialization for Gemini (Linus Walleij)

 - Add missing newlines in the error message in the timers (Rafał Miłecki)

 - Read the clock once and implement the delay timer on Orion (Russell King)
parents 2886a734 6f9c8900

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ stable kernels. 
| ARM            | Cortex-A57      | #852523         | N/A                         |

| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220        |

| ARM            | Cortex-A72      | #853709         | N/A                         |

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

Documentation/devicetree/bindings/timer/cortina,gemini-timer.txt

deleted100644 → 0
+0 −22
Original line number Diff line number Diff line 
Cortina Systems Gemini timer



This timer is embedded in the Cortina Systems Gemini SoCs.



Required properties:



- compatible : Must be "cortina,gemini-timer"

- reg : Should contain registers location and length

- interrupts : Should contain the three timer interrupts with

  flags for rising edge

- syscon : a phandle to the global Gemini system controller



Example:



timer@43000000 {

	compatible = "cortina,gemini-timer";

	reg = <0x43000000 0x1000>;

	interrupts = <14 IRQ_TYPE_EDGE_RISING>, /* Timer 1 */

		   <15 IRQ_TYPE_EDGE_RISING>, /* Timer 2 */

		   <16 IRQ_TYPE_EDGE_RISING>; /* Timer 3 */

	syscon = <&syscon>;

};

Documentation/devicetree/bindings/timer/faraday,fttmr010.txt

0 → 100644
+33 −0
Original line number Diff line number Diff line 
Faraday Technology timer



This timer is a generic IP block from Faraday Technology, embedded in the

Cortina Systems Gemini SoCs and other designs.



Required properties:



- compatible : Must be one of

  "faraday,fttmr010"

  "cortina,gemini-timer"

- reg : Should contain registers location and length

- interrupts : Should contain the three timer interrupts usually with

  flags for falling edge



Optionally required properties:



- clocks : a clock to provide the tick rate for "faraday,fttmr010"

- clock-names : should be "EXTCLK" and "PCLK" for the external tick timer

  and peripheral clock respectively, for "faraday,fttmr010"

- syscon : a phandle to the global Gemini system controller if the compatible

  type is "cortina,gemini-timer"



Example:



timer@43000000 {

	compatible = "faraday,fttmr010";

	reg = <0x43000000 0x1000>;

	interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */

		   <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */

		   <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */

	clocks = <&extclk>, <&pclk>;

	clock-names = "EXTCLK", "PCLK";

};

Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt

+9 −3
Original line number Diff line number Diff line 
Rockchip rk timer



Required properties:

- compatible: shall be one of:

  "rockchip,rk3288-timer" - for rk3066, rk3036, rk3188, rk322x, rk3288, rk3368

  "rockchip,rk3399-timer" - for rk3399

- compatible: should be:

  "rockchip,rk3036-timer", "rockchip,rk3288-timer": for Rockchip RK3036

  "rockchip,rk3066-timer", "rockchip,rk3288-timer": for Rockchip RK3066

  "rockchip,rk3188-timer", "rockchip,rk3288-timer": for Rockchip RK3188

  "rockchip,rk3228-timer", "rockchip,rk3288-timer": for Rockchip RK3228

  "rockchip,rk3229-timer", "rockchip,rk3288-timer": for Rockchip RK3229

  "rockchip,rk3288-timer": for Rockchip RK3288

  "rockchip,rk3368-timer", "rockchip,rk3288-timer": for Rockchip RK3368

  "rockchip,rk3399-timer": for Rockchip RK3399

- reg: base address of the timer register starting with TIMERS CONTROL register

- interrupts: should contain the interrupts for Timer0

- clocks : must contain an entry for each entry in clock-names

arch/arm/boot/dts/rk3188.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -106,6 +106,22 @@ 
		};

	};



	timer3: timer@2000e000 {

		compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";

		reg = <0x2000e000 0x20>;

		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;

		clock-names = "timer", "pclk";

	};



	timer6: timer@200380a0 {

		compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";

		reg = <0x200380a0 0x20>;

		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;

		clock-names = "timer", "pclk";

	};



	i2s0: i2s@1011a000 {

		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";

		reg = <0x1011a000 0x2000>;
@@ -530,6 +546,7 @@ 


&global_timer {

	interrupts = <GIC_PPI 11 0xf04>;

	status = "disabled";

};



&local_timer {

CRA Git | Maintained and supported by SUSTech CRA and CCSE