Commit 6f9c8900 authored by Daniel Lezcano's avatar Daniel Lezcano
Browse files

Merge tag 'arch-timer-errata' of... 

Merge tag 'arch-timer-errata' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms

 into clockevents/4.12

arm64 arch timer workaround series, including the base patches
that will also go via the arm64 tree.

Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
parents 28e71e2f d003d029

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ stable kernels. 
| ARM            | Cortex-A57      | #852523         | N/A                         |

| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220        |

| ARM            | Cortex-A72      | #853709         | N/A                         |

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

arch/arm64/include/asm/arch_timer.h

+32 −11
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include <linux/bug.h>

#include <linux/init.h>

#include <linux/jump_label.h>

#include <linux/smp.h>

#include <linux/types.h>



#include <clocksource/arm_arch_timer.h>
@@ -37,23 +38,43 @@ extern struct static_key_false arch_timer_read_ool_enabled; 
#define needs_unstable_timer_counter_workaround()  false

#endif



enum arch_timer_erratum_match_type {

	ate_match_dt,

	ate_match_local_cap_id,

	ate_match_acpi_oem_info,

};



struct clock_event_device;



struct arch_timer_erratum_workaround {

	const char *id;		/* Indicate the Erratum ID */

	enum arch_timer_erratum_match_type match_type;

	const void *id;

	const char *desc;

	u32 (*read_cntp_tval_el0)(void);

	u32 (*read_cntv_tval_el0)(void);

	u64 (*read_cntvct_el0)(void);

	int (*set_next_event_phys)(unsigned long, struct clock_event_device *);

	int (*set_next_event_virt)(unsigned long, struct clock_event_device *);

};



extern const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround;

DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *,

		timer_unstable_counter_workaround);



#define arch_timer_reg_read_stable(reg)					\

({									\

	u64 _val;							\

	if (needs_unstable_timer_counter_workaround())		\

		_val = timer_unstable_counter_workaround->read_##reg();\

	if (needs_unstable_timer_counter_workaround()) {		\

		const struct arch_timer_erratum_workaround *wa;		\

		preempt_disable();					\

		wa = __this_cpu_read(timer_unstable_counter_workaround); \

		if (wa && wa->read_##reg)				\

			_val = wa->read_##reg();			\

		else							\

			_val = read_sysreg(reg);			\

		preempt_enable();					\

	} else {							\

		_val = read_sysreg(reg);				\

	}								\

	_val;								\

})

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -37,7 +37,8 @@ 
#define ARM64_HAS_NO_FPSIMD			16

#define ARM64_WORKAROUND_REPEAT_TLBI		17

#define ARM64_WORKAROUND_QCOM_FALKOR_E1003	18

#define ARM64_WORKAROUND_858921			19



#define ARM64_NCAPS				19

#define ARM64_NCAPS				20



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ 
#define ARM_CPU_PART_FOUNDATION		0xD00

#define ARM_CPU_PART_CORTEX_A57		0xD07

#define ARM_CPU_PART_CORTEX_A53		0xD03

#define ARM_CPU_PART_CORTEX_A73		0xD09



#define APM_CPU_PART_POTENZA		0x000
@@ -92,6 +93,7 @@ 


#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)

arch/arm64/include/asm/esr.h

+2 −0
Original line number Diff line number Diff line
@@ -175,6 +175,8 @@ 
#define ESR_ELx_SYS64_ISS_SYS_CTR_READ	(ESR_ELx_SYS64_ISS_SYS_CTR | \

					 ESR_ELx_SYS64_ISS_DIR_READ)



#define ESR_ELx_SYS64_ISS_SYS_CNTVCT	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \

					 ESR_ELx_SYS64_ISS_DIR_READ)

#ifndef __ASSEMBLY__

#include <asm/types.h>

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