Commit 81f5090d authored by Yazen Ghannam's avatar Yazen Ghannam Committed by Borislav Petkov
Browse files

EDAC/amd64: Support asymmetric dual-rank DIMMs 



Future AMD systems will support asymmetric dual-rank DIMMs. These are
DIMMs where the ranks are of different sizes.

The even rank will use the Primary Even Chip Select registers and the
odd rank will use the Secondary Odd Chip Select registers.

Recognize if a Secondary Odd Chip Select is being used. Use the
Secondary Odd Address Mask when calculating the chip select size.

 [ bp: move csrow_sec_enabled() to the header, fix CS_ODD define and
   tone-down the capitalized words spelling. ]

Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Tony Luck <tony.luck@intel.com>
Link: https://lkml.kernel.org/r/20190821235938.118710-8-Yazen.Ghannam@amd.com
parent 7574729e

drivers/edac/amd64_edac.c

+13 −3
Original line number Diff line number Diff line
@@ -790,9 +790,11 @@ static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) 


#define CS_EVEN_PRIMARY		BIT(0)

#define CS_ODD_PRIMARY		BIT(1)

#define CS_EVEN_SECONDARY	BIT(2)

#define CS_ODD_SECONDARY	BIT(3)



#define CS_EVEN			CS_EVEN_PRIMARY

#define CS_ODD			CS_ODD_PRIMARY

#define CS_EVEN			(CS_EVEN_PRIMARY | CS_EVEN_SECONDARY)

#define CS_ODD			(CS_ODD_PRIMARY | CS_ODD_SECONDARY)



static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)

{
@@ -804,6 +806,10 @@ static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) 
	if (csrow_enabled(2 * dimm + 1, ctrl, pvt))

		cs_mode |= CS_ODD_PRIMARY;



	/* Asymmetric dual-rank DIMM support. */

	if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt))

		cs_mode |= CS_ODD_SECONDARY;



	return cs_mode;

}
@@ -1600,6 +1606,10 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, 
	 */

	dimm = csrow_nr >> 1;



	/* Asymmetric dual-rank DIMM support. */

	if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))

		addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm];

	else

		addr_mask_orig = pvt->csels[umc].csmasks[dimm];



	/*

drivers/edac/amd64_edac.h

+2 −1
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ 
#define DCSM1				0x160



#define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)]     & DCSB_CS_ENABLE)

#define csrow_sec_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)



#define DRAM_CONTROL			0x78

CRA Git | Maintained and supported by SUSTech CRA and CCSE