clk: aspeed: Add RMII RCLK gates for both AST2500 MACs (801b787a) · Commits · 戴 / test

drivers/clk/clk-aspeed.c

+26 −1

Original line number	Original line	Diff line number	Diff line
	@@ -14,7 +14,7 @@

	#include "clk-aspeed.h"		#include "clk-aspeed.h"

	#define ASPEED_NUM_CLKS 36		#define ASPEED_NUM_CLKS 38

	#define ASPEED_RESET2_OFFSET 32		#define ASPEED_RESET2_OFFSET 32

	@@ -28,6 +28,7 @@
	#define AST2400_HPLL_BYPASS_EN BIT(17)		#define AST2400_HPLL_BYPASS_EN BIT(17)
	#define ASPEED_MISC_CTRL 0x2c		#define ASPEED_MISC_CTRL 0x2c
	#define UART_DIV13_EN BIT(12)		#define UART_DIV13_EN BIT(12)
			#define ASPEED_MAC_CLK_DLY 0x48
	#define ASPEED_STRAP 0x70		#define ASPEED_STRAP 0x70
	#define CLKIN_25MHZ_EN BIT(23)		#define CLKIN_25MHZ_EN BIT(23)
	#define AST2400_CLK_SOURCE_SEL BIT(18)		#define AST2400_CLK_SOURCE_SEL BIT(18)
	@@ -462,6 +463,30 @@ static int aspeed_clk_probe(struct platform_device *pdev)
	return PTR_ERR(hw);		return PTR_ERR(hw);
	aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;		aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;

			if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) {
			/* RMII 50MHz RCLK */
			hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0,
			50000000);
			if (IS_ERR(hw))
			return PTR_ERR(hw);

			/* RMII1 50MHz (RCLK) output enable */
			hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
			scu_base + ASPEED_MAC_CLK_DLY, 29, 0,
			&aspeed_clk_lock);
			if (IS_ERR(hw))
			return PTR_ERR(hw);
			aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;

			/* RMII2 50MHz (RCLK) output enable */
			hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
			scu_base + ASPEED_MAC_CLK_DLY, 30, 0,
			&aspeed_clk_lock);
			if (IS_ERR(hw))
			return PTR_ERR(hw);
			aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
			}

	/* LPC Host (LHCLK) clock divider */		/* LPC Host (LHCLK) clock divider */
	hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,		hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
	scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,		scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,

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